| Line 39... |
Line 39... |
set_global_assignment -name FAMILY "Cyclone II"
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set_global_assignment -name FAMILY "Cyclone II"
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set_global_assignment -name DEVICE EP2C8Q208C8
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set_global_assignment -name DEVICE EP2C8Q208C8
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set_global_assignment -name TOP_LEVEL_ENTITY l80soc
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set_global_assignment -name TOP_LEVEL_ENTITY l80soc
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.1 SP2"
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.1 SP2"
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:57:36 FEBRUARY 17, 2012"
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:57:36 FEBRUARY 17, 2012"
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set_global_assignment -name LAST_QUARTUS_VERSION "9.1 SP2"
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set_global_assignment -name LAST_QUARTUS_VERSION 11.1
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set_global_assignment -name EDA_SIMULATION_TOOL "Custom Verilog HDL"
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set_global_assignment -name EDA_SIMULATION_TOOL "Custom Verilog HDL"
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set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
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set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
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set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
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set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
|
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
|
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
|
set_global_assignment -name SEARCH_PATH ..\\..\\rtl\\verilog\\cores\\rs/
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set_global_assignment -name SEARCH_PATH ..\\..\\rtl\\verilog\\cores\\rs/
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| Line 61... |
Line 61... |
set_global_assignment -name VERILOG_FILE ../../rtl/intr_ctrl.v
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set_global_assignment -name VERILOG_FILE ../../rtl/intr_ctrl.v
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set_global_assignment -name VERILOG_FILE ../../rtl/light8080.v
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set_global_assignment -name VERILOG_FILE ../../rtl/light8080.v
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set_global_assignment -name VERILOG_FILE ../../rtl/micro_rom.v
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set_global_assignment -name VERILOG_FILE ../../rtl/micro_rom.v
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set_global_assignment -name VERILOG_FILE ../../rtl/ram_image.v
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set_global_assignment -name VERILOG_FILE ../../rtl/ram_image.v
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set_global_assignment -name VERILOG_FILE ../../rtl/uart.v
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set_global_assignment -name VERILOG_FILE ../../rtl/uart.v
|
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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