| Line 72... |
Line 72... |
-- Once reset is deasserted, the first fetch at address 0x0000 will happen 4
|
-- Once reset is deasserted, the first fetch at address 0x0000 will happen 4
|
-- cycles later.
|
-- cycles later.
|
--
|
--
|
-- Signal intr is sampled on all positive clock edges. If asserted when inte is
|
-- Signal intr is sampled on all positive clock edges. If asserted when inte is
|
-- high, interrupts will be disabled, inta will be asserted high and a fetch
|
-- high, interrupts will be disabled, inta will be asserted high and a fetch
|
-- cycle will occur. The fetched instruction will be executed normally, except
|
-- cycle will occur immediately after the current instruction ends execution,
|
-- PC will not be valid in any subsequent fetch cycles of the same instruction,
|
-- except if intr was asserted at the last cycle of an instruction. In that case
|
|
-- it will be honored after the next instruction ends.
|
|
-- The fetched instruction will be executed normally, except that PC will not
|
|
-- be valid in any subsequent fetch cycles of the same instruction,
|
-- and will not be incremented (In practice, the same as the original 8080).
|
-- and will not be incremented (In practice, the same as the original 8080).
|
-- inta will remain high for the duration of the fetched instruction (in the
|
-- inta will remain high for the duration of the fetched instruction, including
|
-- original 8080 it was high only for the opcode fetch cycle).
|
-- fetch and execution time (in the original 8080 it was high only for the
|
|
-- opcode fetch cycle).
|
-- PC will not be autoincremented while inta is high, but it can be explicitly
|
-- PC will not be autoincremented while inta is high, but it can be explicitly
|
-- modified (e.g. RTS, CALL, etc.). Again, the same as the original.
|
-- modified (e.g. RST, CALL, etc.). Again, the same as the original.
|
-- Interrupts will be disabled upon assertion of inta, and remain disabled
|
-- Interrupts will be disabled upon assertion of inta, and remain disabled
|
-- until explicitly enabled by the program (as in the original).
|
-- until explicitly enabled by the program (as in the original).
|
|
-- If intr is asserted when inte is low, the interrupt will not be attended but
|
|
-- it will be registered in an int_pending flag, so it will be honored when
|
|
-- interrupts are enabled.
|
|
--
|
--
|
--
|
-- The above means that any instruction can be supplied in an inta cycle,
|
-- The above means that any instruction can be supplied in an inta cycle,
|
-- either single byte or multibyte. See the design notes.
|
-- either single byte or multibyte. See the design notes.
|
--##############################################################################
|
--##############################################################################
|
|
|
| Line 937... |
Line 945... |
end if;
|
end if;
|
end process;
|
end process;
|
|
|
inte <= inte_reg;
|
inte <= inte_reg;
|
|
|
-- interrupts are ignored when inte='0'
|
-- interrupts are ignored when inte='0' but they are registered and will be
|
|
-- honored when interrupts are enabled
|
process(clk)
|
process(clk)
|
begin
|
begin
|
if clk'event and clk='1' then
|
if clk'event and clk='1' then
|
if reset = '1' then
|
if reset = '1' then
|
int_pending <= '0';
|
int_pending <= '0';
|
else
|
else
|
if intr = '1' and inte_reg = '1' and int_pending = '0' then
|
-- intr will raise int_pending only if inta has not been asserted.
|
|
-- Otherwise, if intr overlapped inta, we'd enter a microcode endless
|
|
-- loop, executing the interrupt vector again and again.
|
|
if intr='1' and inte_reg='1' and int_pending='0' and inta_reg='0' then
|
int_pending <= '1';
|
int_pending <= '1';
|
else
|
else
|
|
-- int_pending is cleared when we're about to service the interrupt,
|
|
-- that is when interrupts are enabled and the current instruction ends.
|
if inte_reg = '1' and uc_end='1' then
|
if inte_reg = '1' and uc_end='1' then
|
int_pending <= '0';
|
int_pending <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
| Line 1323... |
Line 1337... |
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
-- 1 2 3 4 5 6 7 8
|
-- 1 2 3 4 5 6 7 8
|
-- __ __ __ __ __ __ __ __
|
-- __ __ __ __ __ __ __ __
|
-- clk __/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__
|
-- clk __/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__
|
--
|
--
|
|
-- ==|=====|=====|=====|=====|=====|=====|=====|=====|
|
|
--
|
-- addr_o xxxxxxxxxxxxxx< ADR >xxxxxxxxxxx< ADR >xxxxxxxxxxx
|
-- addr_o xxxxxxxxxxxxxx< ADR >xxxxxxxxxxx< ADR >xxxxxxxxxxx
|
--
|
--
|
-- data_i xxxxxxxxxxxxxxxxxxxx< Din >xxxxxxxxxxxxxxxxxxxxxxx
|
-- data_i xxxxxxxxxxxxxxxxxxxx< Din >xxxxxxxxxxxxxxxxxxxxxxx
|
--
|
--
|
-- data_o xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx< Dout>xxxxxxxxxxx
|
-- data_o xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx< Dout>xxxxxxxxxxx
|
