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/**************************************
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Author: J.W Tang
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Email: jaytang1987@hotmail.com
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Module: table_reader
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Date: 2016-04-24
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Copyright (C) 2016 J.W. Tang
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----------------------------
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This file is part of LinkRunCCA.
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LinkRunCCA is free software: you can redistribute it and/or modify
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it under the terms of the GNU Lesser General Public License as
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published by the Free Software Foundation, either version 3 of
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the License, or (at your option) any later version.
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LinkRunCCA is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public License
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along with LinkRunCCA. If not, see <http://www.gnu.org/licenses/>.
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By using this component in any associated publication,
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you agree to cite it as:
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Tang, J. W., et al. "A linked list run-length-based single-pass
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connected component analysis for real-time embedded hardware."
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Journal of Real-Time Image Processing: 1-19. 2016.
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doi:10.1007/s11554-016-0590-2.
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***************************************/
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module table_reader(
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module table_reader(
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clk,rst,datavalid, //global input
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clk,rst,datavalid, //global input
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A,B,r1,r2,d,O,HCN, //input from other modules
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A,B,r1,r2,d,O,HCN, //input from other modules
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d_we,d_waddr,h_rdata,t_rdata,n_rdata,d_rdata,h_wdata,t_wdata, //input from table
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d_we,d_waddr,h_rdata,t_rdata,n_rdata,d_rdata,h_wdata,t_wdata, //input from table
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h_raddr,t_raddr,n_raddr,d_raddr, //output to table
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h_raddr,t_raddr,n_raddr,d_raddr, //output to table
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p,hp,np,tp,dp,fp,fn //output to others module
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p,hp,np,tp,dp,fp,fn //output to others module
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);
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);
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parameter address_bit=9;
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parameter address_bit=9;
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parameter data_bit=38;
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parameter data_bit=38;
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input clk,rst,datavalid,A,B,r1,r2,O,HCN,d_we;
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input clk,rst,datavalid,A,B,r1,r2,O,HCN,d_we;
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input [address_bit-1:0]d_waddr,h_rdata,t_rdata,n_rdata,h_wdata,t_wdata;
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input [address_bit-1:0]d_waddr,h_rdata,t_rdata,n_rdata,h_wdata,t_wdata;
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input [data_bit-1:0]d,d_rdata;
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input [data_bit-1:0]d,d_rdata;
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output [address_bit-1:0]n_raddr,h_raddr,t_raddr,d_raddr;
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output [address_bit-1:0]n_raddr,h_raddr,t_raddr,d_raddr;
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output reg [address_bit-1:0]p,hp,np;
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output reg [address_bit-1:0]p,hp,np;
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output [address_bit-1:0]tp;
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output [address_bit-1:0]tp;
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output [data_bit-1:0]dp;
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output [data_bit-1:0]dp;
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output reg fp,fn;
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output reg fp,fn;
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reg [address_bit-1:0]Rtp;
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reg [address_bit-1:0]Rtp;
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reg [data_bit-1:0]Rdp;
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reg [data_bit-1:0]Rdp;
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////label counter p
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////label counter p
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reg [address_bit-1:0]pc;
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reg [address_bit-1:0]pc;
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always@(posedge clk or posedge rst)
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always@(posedge clk or posedge rst)
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if(rst)begin
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if(rst)begin
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pc<=0;p<=0;
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pc<=0;p<=0;
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end
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end
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else if(datavalid)begin
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else if(datavalid)begin
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p<=pc;
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p<=pc;
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if(r1&~r2)begin
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if(r1&~r2)begin
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pc<=pc+1;
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pc<=pc+1;
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end
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end
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end
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end
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//////primary tables
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//////primary tables
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assign n_raddr=pc;
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assign n_raddr=pc;
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assign h_raddr=pc;
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assign h_raddr=pc;
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//////secondary tables
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//////secondary tables
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assign t_raddr=(HCN)?h_wdata:h_rdata;
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assign t_raddr=(HCN)?h_wdata:h_rdata;
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assign d_raddr=(HCN)?h_wdata:h_rdata;
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assign d_raddr=(HCN)?h_wdata:h_rdata;
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//////previous row run cache
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//////previous row run cache
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wire DCN;
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wire DCN;
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assign DCN=(d_we)&(d_waddr==hp);
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assign DCN=(d_we)&(d_waddr==hp);
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assign tp=(~A&B)?t_rdata:Rtp;
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assign tp=(~A&B)?t_rdata:Rtp;
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assign dp=(~A&B)?d_rdata:Rdp;
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assign dp=(~A&B)?d_rdata:Rdp;
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always@(posedge clk or posedge rst)
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always@(posedge clk or posedge rst)
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if(rst)begin
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if(rst)begin
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np<=0;hp<=0;fp<=0;fn<=0;Rtp<=0;Rdp<=0;
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np<=0;hp<=0;fp<=0;fn<=0;Rtp<=0;Rdp<=0;
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end
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end
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else if(datavalid)begin
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else if(datavalid)begin
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Rtp<=tp;Rdp<=dp;
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Rtp<=tp;Rdp<=dp;
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if(DCN)
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if(DCN)
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Rdp<=d;
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Rdp<=d;
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if(~B&r1)begin
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if(~B&r1)begin
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hp<=t_raddr;
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hp<=t_raddr;
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fp<=~(t_raddr==p);
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fp<=~(t_raddr==p);
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np<=n_rdata;
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np<=n_rdata;
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fn<=(n_rdata==p);
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fn<=(n_rdata==p);
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end
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end
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else if(O)begin
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else if(O)begin
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Rtp<=t_wdata;
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Rtp<=t_wdata;
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fp<=1;
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fp<=1;
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hp<=h_wdata;
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hp<=h_wdata;
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end
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end
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end
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end
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endmodule
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endmodule
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