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\section{Interrupt handling}
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\section{Interrupt handling}
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\label{sec:interrupthandling}
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\label{sec:interrupthandling}
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\subsection{Control register}
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\subsection{Control register}
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\lxp{} supports 8 interrupts with hardwired priority levels (interrupts with lower vector numbers have higher priority). Interrupts vectors (pointers to interrupt handlers) are stored in the \code{iv0}--\code{iv7} registers. Interrupt handling is controlled by the \code{cr} register (Table \ref{tab:cr}).
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\lxp{} supports 8 interrupts with hardwired priority levels (interrupts with lower vector numbers have higher priority). Interrupt vectors (pointers to interrupt handlers) are stored in the \code{iv0}--\code{iv7} registers. Interrupt handling is controlled by the \code{cr} register (Table \ref{tab:cr}).
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\begin{table}[htbp]
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\begin{table}[htbp]
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\caption{Control register}
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\caption{Control register}
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\label{tab:cr}
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\label{tab:cr}
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\begin{tabularx}{\textwidth}{lL}
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\begin{tabularx}{\textwidth}{lL}
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\toprule
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\toprule
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Bit & Description \\
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Bit & Description \\
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\midrule
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\midrule
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0 & Enable interrupt 0 \\
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0 & Enable interrupt 0 \\
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1 & Enable interrupt 1 \\
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& \ldots \\
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& \ldots \\
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7 & Enable interrupt 7 \\
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7 & Enable interrupt 7 \\
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8 & Temporarily block interrupt 0 \\
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8 & Interrupt 0 wake-up flag \\
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9 & Temporarily block interrupt 1 \\
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& \ldots \\
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& \ldots \\
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15 & Temporarily block interrupt 7 \\
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15 & Interrupt 7 wake-up flag \\
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31--16 & \emph{Reserved} \\
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31--16 & \emph{Reserved} \\
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\bottomrule
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\bottomrule
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\end{tabularx}
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\end{tabularx}
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\end{table}
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\end{table}
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Disabled interrupts are ignored altogether: if the CPU receives an interrupt request signal while the corresponding interrupt is disabled, the interrupt handler will not be called even if the interrupt is enabled later. Conversely, temporarily blocked interrupts are still registered, but their handlers are not called until they are unblocked.
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Disabled interrupts are ignored altogether: if the CPU receives an interrupt request signal while the corresponding interrupt is disabled, the interrupt will not be processed even if it is enabled later.
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Wake-up flag marks the interrupt as a \emph{wake-up interrupt} (see below).
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Like other registers, \code{cr} is zero-initialized during the CPU reset, meaning that no interrupts are initially enabled.
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Like other registers, \code{cr} is zero-initialized during the CPU reset, meaning that no interrupts are initially enabled.
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\subsection{Invoking interrupt handlers}
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\subsection{Invoking interrupt handlers}
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Interrupt handlers are invoked by the CPU similarly to procedures (Section \ref{sec:callingprocedures}), the difference being that in this case return address is stored in the \code{irp} register (as opposed to \code{rp}), and the least significant bit of the register (\code{IRF} -- \emph{Interrupt Return Flag}) is set.
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Interrupt handlers are invoked by the CPU similarly to procedures (Section \ref{sec:callingprocedures}), the difference being that in this case return address is stored in the \code{irp} register (as opposed to \code{rp}), and the least significant bit of the register (\code{IRF} -- \emph{Interrupt Return Flag}) is set.
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An interrupt handler returns using the \code{\instr{jmp} irp} instruction which also has an \instr{iret} alias. Until the interrupt handler returns, the CPU will defer further interrupt processing (although incoming interrupt requests will still be registered). This also means that the \code{irp} register value will not be unexpectedly overwritten. When executing the \code{\instr{jmp} irp} instruction, the CPU will recognize the \code{IRF} flag and resume interrupt processing as usual. It is also possible to perform a conditional return from the interrupt handler, similarly to the technique described in Section \ref{sec:callingprocedures} for conditional procedure returns.
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An interrupt handler returns using the \code{\instr{jmp} irp} instruction which also has an \instr{iret} alias. Until the interrupt handler returns, the CPU will defer further interrupt processing (although incoming interrupt requests will still be registered). This also means that the \code{irp} register value will not be unexpectedly overwritten. When executing the \code{\instr{jmp} irp} instruction, the CPU will recognize the \code{IRF} flag and resume interrupt processing as usual. It is also possible to perform a conditional return from the interrupt handler, similarly to the technique described in Section \ref{sec:callingprocedures} for conditional procedure returns.
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\subsection{Wake-up interrupts}
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When a wake-up interrupt is received, the interrupt handler is not called, but the CPU still resumes execution if halted by the \instr{hlt} instruction. The effect is similar to invoking an interrupt with an empty handler (containing only \instr{iret}), but without the overhead of interrupt processing. Wake-up interrupts do not affect the CPU when it is not halted.
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Unlike normal interrupts, wake-up interrupts are processed even when the CPU executes an interrupt handler for another interrupt.
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\subsection{Non-returnable interrupts}
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\subsection{Non-returnable interrupts}
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If an interrupt vector has the least significant bit (\code{IRF}) set, the CPU will resume interrupt processing immediately. One should not try to invoke \instr{iret} from such a handler since the \code{irp} register could have been overwritten by another interrupt. This technique can be useful when the CPU's only task is to process external events:
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If an interrupt vector has the least significant bit (\code{IRF}) set, the CPU will resume interrupt processing immediately. One should not try to invoke \instr{iret} from such a handler since the \code{irp} register could have been overwritten by another interrupt. This technique can be useful when the CPU's only task is to process external events:
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\begin{codeparbreakable}
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\begin{codeparbreakable}
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\caption{Typical WISHBONE data bus WRITE and READ cycles}
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\caption{Typical WISHBONE data bus WRITE and READ cycles}
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\label{fig:dbustiming}
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\label{fig:dbustiming}
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\end{figure}
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\end{figure}
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\section{Interrupts}
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\section{Interrupts}
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\label{sec:interrupts}
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\lxp{} registers an interrupt condition when the corresponding request signal goes from \code{0} to \code{1}. Transitions from \code{1} to \code{0} are ignored. All interrupt request signals must be synchronous with the system clock (\signal{clk\_i}); if coming from an asynchronous source, they must be synchronized using a sequence of at least two flip-flops clocked by \signal{clk\_i}. These flip-flops are not included in the \lxp{} core in order not to increase interrupt processing delay for interrupt sources that are inherently synchronous. Failure to properly synchronize interrupt request signals will cause timing violations that will manifest itself as intermittent, hard to debug faults.
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\lxp{} registers an interrupt condition when the corresponding request signal goes from \code{0} to \code{1}. Transitions from \code{1} to \code{0} are ignored. All interrupt request signals must be synchronous with the system clock (\signal{clk\_i}); if coming from an asynchronous source, they must be synchronized using a sequence of at least two flip-flops clocked by \signal{clk\_i}. These flip-flops are not included in the \lxp{} core in order not to increase interrupt processing delay for interrupt sources that are inherently synchronous. Failure to properly synchronize interrupt request signals will cause timing violations that will manifest itself as intermittent, hard to debug faults.
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\section{Synthesis and optimization}
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\section{Synthesis and optimization}
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\label{sec:synthesis}
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\label{sec:synthesis}
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The result is rounded towards zero and is undefined if RD2 is zero. If the CPU was configured without a divider, this instruction returns \code{0}.
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The result is rounded towards zero and is undefined if RD2 is zero. If the CPU was configured without a divider, this instruction returns \code{0}.
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\subsection{\instr{hlt} -- Halt}
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\subsection{\instr{hlt} -- Halt}
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\label{subsec:instr:hlt}
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\label{subsec:instr:hlt}
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Wait for an interrupt.
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Halt the CPU until an enabled interrupt is received.
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\subsubsection{Syntax}
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\subsubsection{Syntax}
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\code{\instr{hlt}}
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\code{\instr{hlt}}
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\bottomrule
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\bottomrule
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\end{ctabular}
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\end{ctabular}
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\chapter{List of changes}
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\chapter{List of changes}
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\section*{Version 1.3 (2022-08-28)}
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This release removes support for temporarily blocked interrupts (interrupts can still be disabled) and introduces wake-up interrupts.
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\section*{Version 1.2 (2021-10-21)}
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\section*{Version 1.2 (2021-10-21)}
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This release introduces a few non-breaking changes to the software and testbench. The CPU RTL description hasn't been changed from the previous release.
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This release introduces a few non-breaking changes to the software and testbench. The CPU RTL description hasn't been changed from the previous release.
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\begin{itemize}
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\begin{itemize}
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