| Line 29... |
Line 29... |
cmd_div_i: in std_logic;
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cmd_div_i: in std_logic;
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cmd_div_mod_i: in std_logic;
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cmd_div_mod_i: in std_logic;
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cmd_cmp_i: in std_logic;
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cmd_cmp_i: in std_logic;
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cmd_negate_op2_i: in std_logic;
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cmd_negate_op2_i: in std_logic;
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cmd_and_i: in std_logic;
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cmd_and_i: in std_logic;
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cmd_or_i: in std_logic;
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cmd_xor_i: in std_logic;
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cmd_xor_i: in std_logic;
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cmd_shift_i: in std_logic;
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cmd_shift_i: in std_logic;
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cmd_shift_right_i: in std_logic;
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cmd_shift_right_i: in std_logic;
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op1_i: in std_logic_vector(31 downto 0);
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op1_i: in std_logic_vector(31 downto 0);
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| Line 60... |
Line 59... |
signal cmp_eq: std_logic;
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signal cmp_eq: std_logic;
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signal cmp_carry: std_logic;
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signal cmp_carry: std_logic;
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signal cmp_s1: std_logic;
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signal cmp_s1: std_logic;
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signal cmp_s2: std_logic;
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signal cmp_s2: std_logic;
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signal and_result: std_logic_vector(31 downto 0);
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signal logic_result: std_logic_vector(31 downto 0);
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signal and_we: std_logic;
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signal logic_we: std_logic;
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signal or_result: std_logic_vector(31 downto 0);
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signal or_we: std_logic;
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signal xor_result: std_logic_vector(31 downto 0);
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signal xor_we: std_logic;
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signal mul_result: std_logic_vector(31 downto 0);
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signal mul_result: std_logic_vector(31 downto 0);
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signal mul_ce: std_logic;
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signal mul_ce: std_logic;
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signal mul_we: std_logic;
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signal mul_we: std_logic;
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signal div_quotient: std_logic_vector(31 downto 0);
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signal div_result: std_logic_vector(31 downto 0);
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signal div_remainder: std_logic_vector(31 downto 0);
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signal div_ce: std_logic;
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signal div_ce: std_logic;
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signal div_we: std_logic;
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signal div_we: std_logic;
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signal div_select_remainder: std_logic;
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signal shift_result: std_logic_vector(31 downto 0);
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signal shift_result: std_logic_vector(31 downto 0);
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signal shift_ce: std_logic;
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signal shift_ce: std_logic;
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signal shift_we: std_logic;
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signal shift_we: std_logic;
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| Line 95... |
Line 88... |
severity failure;
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severity failure;
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-- Add/subtract
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-- Add/subtract
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addend1<=unsigned(op1_i);
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addend1<=unsigned(op1_i);
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addend2<=unsigned(op2_i) when cmd_negate_op2_i='0' else not unsigned(op2_i);
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addend2_gen: for i in addend2'range generate
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addend2(i)<=op2_i(i) xor cmd_negate_op2_i;
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end generate;
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adder_result<=("0"&addend1)+("0"&addend2)+(to_unsigned(0,adder_result'length-1)&cmd_negate_op2_i);
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adder_result<=("0"&addend1)+("0"&addend2)+(to_unsigned(0,adder_result'length-1)&cmd_negate_op2_i);
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adder_we<=cmd_addsub_i and valid_i;
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adder_we<=cmd_addsub_i and valid_i;
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-- Comparator (needs cmd_negate_op2_i to work correctly)
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-- Comparator (needs cmd_negate_op2_i to work correctly)
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| Line 124... |
Line 121... |
cmp_ug_o<=cmp_carry and not cmp_eq;
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cmp_ug_o<=cmp_carry and not cmp_eq;
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cmp_sg_o<=((cmp_s1 and cmp_s2 and cmp_carry) or
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cmp_sg_o<=((cmp_s1 and cmp_s2 and cmp_carry) or
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(not cmp_s1 and not cmp_s2 and cmp_carry) or
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(not cmp_s1 and not cmp_s2 and cmp_carry) or
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(not cmp_s1 and cmp_s2)) and not cmp_eq;
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(not cmp_s1 and cmp_s2)) and not cmp_eq;
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-- Logical functions
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-- Bitwise operations (and, or, xor)
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-- Note: (a or b) = (a and b) or (a xor b)
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logic_result_gen: for i in logic_result'range generate
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logic_result(i)<=((op1_i(i) and op2_i(i)) and cmd_and_i) or
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((op1_i(i) xor op2_i(i)) and cmd_xor_i);
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end generate;
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and_result<=op1_i and op2_i;
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logic_we<=(cmd_and_i or cmd_xor_i) and valid_i;
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and_we<=cmd_and_i and valid_i;
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or_result<=op1_i or op2_i;
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or_we<=cmd_or_i and valid_i;
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xor_result<=op1_i xor op2_i;
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xor_we<=cmd_xor_i and valid_i;
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-- Multiplier
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-- Multiplier
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mul_ce<=cmd_mul_i and valid_i;
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mul_ce<=cmd_mul_i and valid_i;
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| Line 189... |
Line 187... |
rst_i=>rst_i,
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rst_i=>rst_i,
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ce_i=>div_ce,
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ce_i=>div_ce,
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op1_i=>op1_i,
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op1_i=>op1_i,
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op2_i=>op2_i,
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op2_i=>op2_i,
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signed_i=>cmd_signed_i,
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signed_i=>cmd_signed_i,
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rem_i=>cmd_div_mod_i,
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ce_o=>div_we,
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ce_o=>div_we,
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quotient_o=>div_quotient,
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result_o=>div_result
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remainder_o=>div_remainder
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);
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);
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end generate;
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end generate;
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gen_no_divider: if not DIVIDER_EN generate
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gen_no_divider: if not DIVIDER_EN generate
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div_we<=div_ce;
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div_we<=div_ce;
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div_quotient<=(others=>'0');
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div_result<=(others=>'0');
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div_remainder<=(others=>'0');
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end generate;
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end generate;
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process (clk_i) is
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begin
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if rising_edge(clk_i) then
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if div_ce='1' then
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div_select_remainder<=cmd_div_mod_i;
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end if;
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end if;
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end process;
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-- Shifter
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-- Shifter
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shift_ce<=cmd_shift_i and valid_i;
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shift_ce<=cmd_shift_i and valid_i;
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shifter_inst: entity work.lxp32_shifter(rtl)
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shifter_inst: entity work.lxp32_shifter(rtl)
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| Line 231... |
Line 219... |
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-- Result multiplexer
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-- Result multiplexer
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result_mux_gen: for i in result_mux'range generate
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result_mux_gen: for i in result_mux'range generate
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result_mux(i)<=(adder_result(i) and adder_we) or
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result_mux(i)<=(adder_result(i) and adder_we) or
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(and_result(i) and and_we) or
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(logic_result(i) and logic_we) or
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(or_result(i) and or_we) or
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(xor_result(i) and xor_we) or
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(mul_result(i) and mul_we) or
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(mul_result(i) and mul_we) or
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(div_quotient(i) and div_we and not div_select_remainder) or
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(div_result(i) and div_we) or
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(div_remainder(i) and div_we and div_select_remainder) or
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(shift_result(i) and shift_we);
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(shift_result(i) and shift_we);
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end generate;
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end generate;
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result_o<=result_mux;
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result_o<=result_mux;
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result_we<=adder_we or and_we or or_we or xor_we or mul_we or div_we or shift_we;
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result_we<=adder_we or logic_we or mul_we or div_we or shift_we;
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we_o<=result_we;
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we_o<=result_we;
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-- Pipeline control
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-- Pipeline control
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process (clk_i) is
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process (clk_i) is
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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if rst_i='1' then
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if rst_i='1' or result_we='1' then
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busy<='0';
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busy<='0';
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else
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elsif shift_ce='1' or mul_ce='1' or div_ce='1' then
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if shift_ce='1' or mul_ce='1' or div_ce='1' then
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busy<='1';
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busy<='1';
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end if;
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end if;
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if result_we='1' then
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busy<='0';
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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busy_o<=busy;
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busy_o<=busy;
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