---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- LXP32 CPU Core
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-- LXP32 CPU Core
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--
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--
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-- Part of the LXP32 CPU
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-- Part of the LXP32 CPU
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--
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--
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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entity lxp32_cpu is
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entity lxp32_cpu is
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generic(
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generic(
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DBUS_RMW: boolean;
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DBUS_RMW: boolean;
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DIVIDER_EN: boolean;
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DIVIDER_EN: boolean;
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MUL_ARCH: string;
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MUL_ARCH: string;
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START_ADDR: std_logic_vector(31 downto 0)
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START_ADDR: std_logic_vector(31 downto 0)
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);
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);
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port(
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port(
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clk_i: in std_logic;
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clk_i: in std_logic;
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rst_i: in std_logic;
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rst_i: in std_logic;
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lli_re_o: out std_logic;
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lli_re_o: out std_logic;
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lli_adr_o: out std_logic_vector(29 downto 0);
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lli_adr_o: out std_logic_vector(29 downto 0);
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lli_dat_i: in std_logic_vector(31 downto 0);
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lli_dat_i: in std_logic_vector(31 downto 0);
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lli_busy_i: in std_logic;
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lli_busy_i: in std_logic;
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dbus_cyc_o: out std_logic;
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dbus_cyc_o: out std_logic;
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dbus_stb_o: out std_logic;
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dbus_stb_o: out std_logic;
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dbus_we_o: out std_logic;
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dbus_we_o: out std_logic;
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dbus_sel_o: out std_logic_vector(3 downto 0);
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dbus_sel_o: out std_logic_vector(3 downto 0);
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dbus_ack_i: in std_logic;
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dbus_ack_i: in std_logic;
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dbus_adr_o: out std_logic_vector(31 downto 2);
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dbus_adr_o: out std_logic_vector(31 downto 2);
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dbus_dat_o: out std_logic_vector(31 downto 0);
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dbus_dat_o: out std_logic_vector(31 downto 0);
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dbus_dat_i: in std_logic_vector(31 downto 0);
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dbus_dat_i: in std_logic_vector(31 downto 0);
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irq_i: in std_logic_vector(7 downto 0)
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irq_i: in std_logic_vector(7 downto 0)
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);
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);
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end entity;
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end entity;
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architecture rtl of lxp32_cpu is
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architecture rtl of lxp32_cpu is
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signal fetch_word: std_logic_vector(31 downto 0);
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signal fetch_word: std_logic_vector(31 downto 0);
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signal fetch_next_ip: std_logic_vector(29 downto 0);
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signal fetch_next_ip: std_logic_vector(29 downto 0);
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signal fetch_current_ip: std_logic_vector(29 downto 0);
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signal fetch_current_ip: std_logic_vector(29 downto 0);
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signal fetch_valid: std_logic;
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signal fetch_valid: std_logic;
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signal fetch_jump_ready: std_logic;
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signal fetch_jump_ready: std_logic;
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signal decode_ready: std_logic;
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signal decode_ready: std_logic;
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signal decode_valid: std_logic;
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signal decode_valid: std_logic;
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signal decode_cmd_loadop3: std_logic;
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signal decode_cmd_loadop3: std_logic;
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signal decode_cmd_signed: std_logic;
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signal decode_cmd_signed: std_logic;
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signal decode_cmd_dbus: std_logic;
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signal decode_cmd_dbus: std_logic;
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signal decode_cmd_dbus_store: std_logic;
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signal decode_cmd_dbus_store: std_logic;
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signal decode_cmd_dbus_byte: std_logic;
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signal decode_cmd_dbus_byte: std_logic;
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signal decode_cmd_addsub: std_logic;
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signal decode_cmd_addsub: std_logic;
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signal decode_cmd_mul: std_logic;
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signal decode_cmd_mul: std_logic;
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signal decode_cmd_div: std_logic;
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signal decode_cmd_div: std_logic;
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signal decode_cmd_div_mod: std_logic;
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signal decode_cmd_div_mod: std_logic;
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signal decode_cmd_cmp: std_logic;
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signal decode_cmd_cmp: std_logic;
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signal decode_cmd_jump: std_logic;
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signal decode_cmd_jump: std_logic;
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signal decode_cmd_negate_op2: std_logic;
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signal decode_cmd_negate_op2: std_logic;
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signal decode_cmd_and: std_logic;
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signal decode_cmd_and: std_logic;
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signal decode_cmd_xor: std_logic;
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signal decode_cmd_xor: std_logic;
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signal decode_cmd_shift: std_logic;
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signal decode_cmd_shift: std_logic;
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signal decode_cmd_shift_right: std_logic;
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signal decode_cmd_shift_right: std_logic;
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signal decode_jump_type: std_logic_vector(3 downto 0);
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signal decode_jump_type: std_logic_vector(3 downto 0);
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signal decode_op1: std_logic_vector(31 downto 0);
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signal decode_op1: std_logic_vector(31 downto 0);
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signal decode_op2: std_logic_vector(31 downto 0);
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signal decode_op2: std_logic_vector(31 downto 0);
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signal decode_op3: std_logic_vector(31 downto 0);
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signal decode_op3: std_logic_vector(31 downto 0);
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signal decode_dst: std_logic_vector(7 downto 0);
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signal decode_dst: std_logic_vector(7 downto 0);
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signal execute_ready: std_logic;
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signal execute_ready: std_logic;
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signal execute_jump_valid: std_logic;
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signal execute_jump_valid: std_logic;
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signal execute_jump_dst: std_logic_vector(29 downto 0);
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signal execute_jump_dst: std_logic_vector(29 downto 0);
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signal sp_raddr1: std_logic_vector(7 downto 0);
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signal sp_raddr1: std_logic_vector(7 downto 0);
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signal sp_rdata1: std_logic_vector(31 downto 0);
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signal sp_rdata1: std_logic_vector(31 downto 0);
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signal sp_raddr2: std_logic_vector(7 downto 0);
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signal sp_raddr2: std_logic_vector(7 downto 0);
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signal sp_rdata2: std_logic_vector(31 downto 0);
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signal sp_rdata2: std_logic_vector(31 downto 0);
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signal sp_waddr: std_logic_vector(7 downto 0);
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signal sp_waddr: std_logic_vector(7 downto 0);
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signal sp_we: std_logic;
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signal sp_we: std_logic;
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signal sp_wdata: std_logic_vector(31 downto 0);
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signal sp_wdata: std_logic_vector(31 downto 0);
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signal interrupt_valid: std_logic;
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signal interrupt_valid: std_logic;
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signal interrupt_vector: std_logic_vector(2 downto 0);
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signal interrupt_vector: std_logic_vector(2 downto 0);
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signal interrupt_ready: std_logic;
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signal interrupt_ready: std_logic;
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signal interrupt_return: std_logic;
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signal interrupt_return: std_logic;
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begin
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begin
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fetch_inst: entity work.lxp32_fetch(rtl)
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fetch_inst: entity work.lxp32_fetch(rtl)
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generic map(
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generic map(
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START_ADDR=>START_ADDR
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START_ADDR=>START_ADDR
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)
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)
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port map(
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port map(
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clk_i=>clk_i,
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clk_i=>clk_i,
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rst_i=>rst_i,
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rst_i=>rst_i,
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lli_re_o=>lli_re_o,
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lli_re_o=>lli_re_o,
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lli_adr_o=>lli_adr_o,
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lli_adr_o=>lli_adr_o,
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lli_dat_i=>lli_dat_i,
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lli_dat_i=>lli_dat_i,
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lli_busy_i=>lli_busy_i,
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lli_busy_i=>lli_busy_i,
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word_o=>fetch_word,
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word_o=>fetch_word,
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next_ip_o=>fetch_next_ip,
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next_ip_o=>fetch_next_ip,
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current_ip_o=>fetch_current_ip,
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current_ip_o=>fetch_current_ip,
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valid_o=>fetch_valid,
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valid_o=>fetch_valid,
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ready_i=>decode_ready,
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ready_i=>decode_ready,
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jump_valid_i=>execute_jump_valid,
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jump_valid_i=>execute_jump_valid,
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jump_dst_i=>execute_jump_dst,
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jump_dst_i=>execute_jump_dst,
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jump_ready_o=>fetch_jump_ready
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jump_ready_o=>fetch_jump_ready
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);
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);
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decode_inst: entity work.lxp32_decode(rtl)
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decode_inst: entity work.lxp32_decode(rtl)
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port map(
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port map(
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clk_i=>clk_i,
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clk_i=>clk_i,
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rst_i=>rst_i,
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rst_i=>rst_i,
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word_i=>fetch_word,
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word_i=>fetch_word,
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next_ip_i=>fetch_next_ip,
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next_ip_i=>fetch_next_ip,
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current_ip_i=>fetch_current_ip,
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current_ip_i=>fetch_current_ip,
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valid_i=>fetch_valid,
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valid_i=>fetch_valid,
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jump_valid_i=>execute_jump_valid,
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jump_valid_i=>execute_jump_valid,
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ready_o=>decode_ready,
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ready_o=>decode_ready,
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interrupt_valid_i=>interrupt_valid,
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interrupt_valid_i=>interrupt_valid,
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interrupt_vector_i=>interrupt_vector,
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interrupt_vector_i=>interrupt_vector,
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interrupt_ready_o=>interrupt_ready,
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interrupt_ready_o=>interrupt_ready,
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sp_raddr1_o=>sp_raddr1,
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sp_raddr1_o=>sp_raddr1,
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sp_rdata1_i=>sp_rdata1,
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sp_rdata1_i=>sp_rdata1,
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sp_raddr2_o=>sp_raddr2,
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sp_raddr2_o=>sp_raddr2,
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sp_rdata2_i=>sp_rdata2,
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sp_rdata2_i=>sp_rdata2,
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ready_i=>execute_ready,
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ready_i=>execute_ready,
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valid_o=>decode_valid,
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valid_o=>decode_valid,
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cmd_loadop3_o=>decode_cmd_loadop3,
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cmd_loadop3_o=>decode_cmd_loadop3,
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cmd_signed_o=>decode_cmd_signed,
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cmd_signed_o=>decode_cmd_signed,
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cmd_dbus_o=>decode_cmd_dbus,
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cmd_dbus_o=>decode_cmd_dbus,
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cmd_dbus_store_o=>decode_cmd_dbus_store,
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cmd_dbus_store_o=>decode_cmd_dbus_store,
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cmd_dbus_byte_o=>decode_cmd_dbus_byte,
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cmd_dbus_byte_o=>decode_cmd_dbus_byte,
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cmd_addsub_o=>decode_cmd_addsub,
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cmd_addsub_o=>decode_cmd_addsub,
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cmd_mul_o=>decode_cmd_mul,
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cmd_mul_o=>decode_cmd_mul,
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cmd_div_o=>decode_cmd_div,
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cmd_div_o=>decode_cmd_div,
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cmd_div_mod_o=>decode_cmd_div_mod,
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cmd_div_mod_o=>decode_cmd_div_mod,
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cmd_cmp_o=>decode_cmd_cmp,
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cmd_cmp_o=>decode_cmd_cmp,
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cmd_jump_o=>decode_cmd_jump,
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cmd_jump_o=>decode_cmd_jump,
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cmd_negate_op2_o=>decode_cmd_negate_op2,
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cmd_negate_op2_o=>decode_cmd_negate_op2,
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cmd_and_o=>decode_cmd_and,
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cmd_and_o=>decode_cmd_and,
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cmd_xor_o=>decode_cmd_xor,
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cmd_xor_o=>decode_cmd_xor,
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cmd_shift_o=>decode_cmd_shift,
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cmd_shift_o=>decode_cmd_shift,
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cmd_shift_right_o=>decode_cmd_shift_right,
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cmd_shift_right_o=>decode_cmd_shift_right,
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jump_type_o=>decode_jump_type,
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jump_type_o=>decode_jump_type,
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op1_o=>decode_op1,
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op1_o=>decode_op1,
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op2_o=>decode_op2,
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op2_o=>decode_op2,
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op3_o=>decode_op3,
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op3_o=>decode_op3,
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dst_o=>decode_dst
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dst_o=>decode_dst
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);
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);
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execute_inst: entity work.lxp32_execute(rtl)
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execute_inst: entity work.lxp32_execute(rtl)
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generic map(
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generic map(
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DBUS_RMW=>DBUS_RMW,
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DBUS_RMW=>DBUS_RMW,
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DIVIDER_EN=>DIVIDER_EN,
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DIVIDER_EN=>DIVIDER_EN,
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MUL_ARCH=>MUL_ARCH
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MUL_ARCH=>MUL_ARCH
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)
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)
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port map(
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port map(
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clk_i=>clk_i,
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clk_i=>clk_i,
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rst_i=>rst_i,
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rst_i=>rst_i,
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cmd_loadop3_i=>decode_cmd_loadop3,
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cmd_loadop3_i=>decode_cmd_loadop3,
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cmd_signed_i=>decode_cmd_signed,
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cmd_signed_i=>decode_cmd_signed,
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cmd_dbus_i=>decode_cmd_dbus,
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cmd_dbus_i=>decode_cmd_dbus,
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cmd_dbus_store_i=>decode_cmd_dbus_store,
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cmd_dbus_store_i=>decode_cmd_dbus_store,
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cmd_dbus_byte_i=>decode_cmd_dbus_byte,
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cmd_dbus_byte_i=>decode_cmd_dbus_byte,
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cmd_addsub_i=>decode_cmd_addsub,
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cmd_addsub_i=>decode_cmd_addsub,
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cmd_mul_i=>decode_cmd_mul,
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cmd_mul_i=>decode_cmd_mul,
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cmd_div_i=>decode_cmd_div,
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cmd_div_i=>decode_cmd_div,
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cmd_div_mod_i=>decode_cmd_div_mod,
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cmd_div_mod_i=>decode_cmd_div_mod,
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cmd_cmp_i=>decode_cmd_cmp,
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cmd_cmp_i=>decode_cmd_cmp,
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cmd_jump_i=>decode_cmd_jump,
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cmd_jump_i=>decode_cmd_jump,
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cmd_negate_op2_i=>decode_cmd_negate_op2,
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cmd_negate_op2_i=>decode_cmd_negate_op2,
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cmd_and_i=>decode_cmd_and,
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cmd_and_i=>decode_cmd_and,
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cmd_xor_i=>decode_cmd_xor,
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cmd_xor_i=>decode_cmd_xor,
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cmd_shift_i=>decode_cmd_shift,
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cmd_shift_i=>decode_cmd_shift,
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cmd_shift_right_i=>decode_cmd_shift_right,
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cmd_shift_right_i=>decode_cmd_shift_right,
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|
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jump_type_i=>decode_jump_type,
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jump_type_i=>decode_jump_type,
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op1_i=>decode_op1,
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op1_i=>decode_op1,
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op2_i=>decode_op2,
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op2_i=>decode_op2,
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op3_i=>decode_op3,
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op3_i=>decode_op3,
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dst_i=>decode_dst,
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dst_i=>decode_dst,
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|
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sp_waddr_o=>sp_waddr,
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sp_waddr_o=>sp_waddr,
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sp_we_o=>sp_we,
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sp_we_o=>sp_we,
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sp_wdata_o=>sp_wdata,
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sp_wdata_o=>sp_wdata,
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|
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valid_i=>decode_valid,
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valid_i=>decode_valid,
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ready_o=>execute_ready,
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ready_o=>execute_ready,
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|
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dbus_cyc_o=>dbus_cyc_o,
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dbus_cyc_o=>dbus_cyc_o,
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dbus_stb_o=>dbus_stb_o,
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dbus_stb_o=>dbus_stb_o,
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dbus_we_o=>dbus_we_o,
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dbus_we_o=>dbus_we_o,
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dbus_sel_o=>dbus_sel_o,
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dbus_sel_o=>dbus_sel_o,
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dbus_ack_i=>dbus_ack_i,
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dbus_ack_i=>dbus_ack_i,
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dbus_adr_o=>dbus_adr_o,
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dbus_adr_o=>dbus_adr_o,
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dbus_dat_o=>dbus_dat_o,
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dbus_dat_o=>dbus_dat_o,
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dbus_dat_i=>dbus_dat_i,
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dbus_dat_i=>dbus_dat_i,
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|
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jump_valid_o=>execute_jump_valid,
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jump_valid_o=>execute_jump_valid,
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jump_dst_o=>execute_jump_dst,
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jump_dst_o=>execute_jump_dst,
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jump_ready_i=>fetch_jump_ready,
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jump_ready_i=>fetch_jump_ready,
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|
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interrupt_return_o=>interrupt_return
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interrupt_return_o=>interrupt_return
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);
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);
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scratchpad_inst: entity work.lxp32_scratchpad(rtl)
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scratchpad_inst: entity work.lxp32_scratchpad(rtl)
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port map(
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port map(
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clk_i=>clk_i,
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clk_i=>clk_i,
|
|
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raddr1_i=>sp_raddr1,
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raddr1_i=>sp_raddr1,
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rdata1_o=>sp_rdata1,
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rdata1_o=>sp_rdata1,
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raddr2_i=>sp_raddr2,
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raddr2_i=>sp_raddr2,
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rdata2_o=>sp_rdata2,
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rdata2_o=>sp_rdata2,
|
|
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waddr_i=>sp_waddr,
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waddr_i=>sp_waddr,
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we_i=>sp_we,
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we_i=>sp_we,
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wdata_i=>sp_wdata
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wdata_i=>sp_wdata
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);
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);
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|
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interrupt_mux_inst: entity work.lxp32_interrupt_mux(rtl)
|
interrupt_mux_inst: entity work.lxp32_interrupt_mux(rtl)
|
port map(
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port map(
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clk_i=>clk_i,
|
clk_i=>clk_i,
|
rst_i=>rst_i,
|
rst_i=>rst_i,
|
|
|
irq_i=>irq_i,
|
irq_i=>irq_i,
|
|
|
interrupt_valid_o=>interrupt_valid,
|
interrupt_valid_o=>interrupt_valid,
|
interrupt_vector_o=>interrupt_vector,
|
interrupt_vector_o=>interrupt_vector,
|
interrupt_ready_i=>interrupt_ready,
|
interrupt_ready_i=>interrupt_ready,
|
interrupt_return_i=>interrupt_return,
|
interrupt_return_i=>interrupt_return,
|
|
|
sp_waddr_i=>sp_waddr,
|
sp_waddr_i=>sp_waddr,
|
sp_we_i=>sp_we,
|
sp_we_i=>sp_we,
|
sp_wdata_i=>sp_wdata
|
sp_wdata_i=>sp_wdata
|
);
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);
|
|
|
end architecture;
|
end architecture;
|
|
|
