---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- DBUS master
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-- DBUS master
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--
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--
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-- Part of the LXP32 CPU
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-- Part of the LXP32 CPU
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--
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--
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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--
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--
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-- Manages data bus (DBUS) access.
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-- Manages data bus (DBUS) access.
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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entity lxp32_dbus is
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entity lxp32_dbus is
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generic(
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generic(
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RMW: boolean
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RMW: boolean
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);
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);
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port(
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port(
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clk_i: in std_logic;
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clk_i: in std_logic;
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rst_i: in std_logic;
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rst_i: in std_logic;
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valid_i: in std_logic;
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valid_i: in std_logic;
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cmd_dbus_i: in std_logic;
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cmd_dbus_i: in std_logic;
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cmd_dbus_store_i: in std_logic;
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cmd_dbus_store_i: in std_logic;
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cmd_dbus_byte_i: in std_logic;
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cmd_dbus_byte_i: in std_logic;
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cmd_signed_i: in std_logic;
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cmd_signed_i: in std_logic;
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addr_i: in std_logic_vector(31 downto 0);
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addr_i: in std_logic_vector(31 downto 0);
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wdata_i: in std_logic_vector(31 downto 0);
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wdata_i: in std_logic_vector(31 downto 0);
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rdata_o: out std_logic_vector(31 downto 0);
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rdata_o: out std_logic_vector(31 downto 0);
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we_o: out std_logic;
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we_o: out std_logic;
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busy_o: out std_logic;
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busy_o: out std_logic;
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dbus_cyc_o: out std_logic;
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dbus_cyc_o: out std_logic;
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dbus_stb_o: out std_logic;
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dbus_stb_o: out std_logic;
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dbus_we_o: out std_logic;
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dbus_we_o: out std_logic;
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dbus_sel_o: out std_logic_vector(3 downto 0);
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dbus_sel_o: out std_logic_vector(3 downto 0);
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dbus_ack_i: in std_logic;
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dbus_ack_i: in std_logic;
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dbus_adr_o: out std_logic_vector(31 downto 2);
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dbus_adr_o: out std_logic_vector(31 downto 2);
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dbus_dat_o: out std_logic_vector(31 downto 0);
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dbus_dat_o: out std_logic_vector(31 downto 0);
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dbus_dat_i: in std_logic_vector(31 downto 0)
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dbus_dat_i: in std_logic_vector(31 downto 0)
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);
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);
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end entity;
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end entity;
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architecture rtl of lxp32_dbus is
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architecture rtl of lxp32_dbus is
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signal strobe: std_logic:='0';
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signal strobe: std_logic:='0';
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signal we_out: std_logic:='0';
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signal we_out: std_logic:='0';
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signal we: std_logic;
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signal we: std_logic;
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signal byte_mode: std_logic;
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signal byte_mode: std_logic;
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signal sel: std_logic_vector(3 downto 0);
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signal sel: std_logic_vector(3 downto 0);
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signal sig: std_logic;
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signal sig: std_logic;
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signal rmw_mode: std_logic;
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signal rmw_mode: std_logic;
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signal dbus_rdata: std_logic_vector(31 downto 0);
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signal selected_byte: std_logic_vector(7 downto 0);
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signal selected_byte: std_logic_vector(7 downto 0);
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begin
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begin
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process (clk_i) is
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process (clk_i) is
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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if rst_i='1' then
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if rst_i='1' then
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we_out<='0';
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we_out<='0';
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strobe<='0';
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strobe<='0';
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sig<='-';
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byte_mode<='-';
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sel<=(others=>'-');
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we<='-';
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rmw_mode<='-';
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dbus_adr_o<=(others=>'-');
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dbus_dat_o<=(others=>'-');
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else
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else
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we_out<='0';
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we_out<='0';
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if strobe='0' then
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if strobe='0' then
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if valid_i='1' and cmd_dbus_i='1' then
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if valid_i='1' and cmd_dbus_i='1' then
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strobe<='1';
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strobe<='1';
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sig<=cmd_signed_i;
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sig<=cmd_signed_i;
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dbus_adr_o<=addr_i(31 downto 2);
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dbus_adr_o<=addr_i(31 downto 2);
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dbus_dat_o<=wdata_i;
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if cmd_dbus_byte_i='0' then
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if cmd_dbus_byte_i='0' then
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byte_mode<='0';
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byte_mode<='0';
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dbus_dat_o<=wdata_i;
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sel<="1111";
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sel<="1111";
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-- synthesis translate_off
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-- synthesis translate_off
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assert addr_i(1 downto 0)="00"
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assert addr_i(1 downto 0)="00"
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report "Misaligned word-granular access on data bus"
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report "Misaligned word-granular access on data bus"
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severity warning;
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severity warning;
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-- synthesis translate_on
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-- synthesis translate_on
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else
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else
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byte_mode<='1';
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byte_mode<='1';
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dbus_dat_o<=wdata_i(7 downto 0)&wdata_i(7 downto 0)&
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wdata_i(7 downto 0)&wdata_i(7 downto 0);
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case addr_i(1 downto 0) is
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case addr_i(1 downto 0) is
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when "00" => sel<="0001"; dbus_dat_o(7 downto 0)<=wdata_i(7 downto 0);
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when "00" => sel<="0001";
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when "01" => sel<="0010"; dbus_dat_o(15 downto 8)<=wdata_i(7 downto 0);
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when "01" => sel<="0010";
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when "10" => sel<="0100"; dbus_dat_o(23 downto 16)<=wdata_i(7 downto 0);
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when "10" => sel<="0100";
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when "11" => sel<="1000"; dbus_dat_o(31 downto 24)<=wdata_i(7 downto 0);
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when "11" => sel<="1000";
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when others =>
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when others =>
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end case;
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end case;
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end if;
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end if;
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if not RMW then
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if not RMW then
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we<=cmd_dbus_store_i;
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we<=cmd_dbus_store_i;
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rmw_mode<='0';
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rmw_mode<='0';
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else
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else
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we<=cmd_dbus_store_i and not cmd_dbus_byte_i;
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we<=cmd_dbus_store_i and not cmd_dbus_byte_i;
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rmw_mode<=cmd_dbus_store_i and cmd_dbus_byte_i;
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rmw_mode<=cmd_dbus_store_i and cmd_dbus_byte_i;
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end if;
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end if;
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end if;
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end if;
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else
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else
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if dbus_ack_i='1' then
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if dbus_ack_i='1' then
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if rmw_mode='1' and we='0' and RMW then
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if rmw_mode='1' and we='0' and RMW then
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we<='1';
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we<='1';
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for i in sel'range loop
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for i in sel'range loop
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if sel(i)='0' then
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if sel(i)='0' then
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dbus_dat_o(i*8+7 downto i*8)<=
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dbus_dat_o(i*8+7 downto i*8)<=
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dbus_dat_i(i*8+7 downto i*8);
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dbus_dat_i(i*8+7 downto i*8);
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end if;
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end if;
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end loop;
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end loop;
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else
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else
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strobe<='0';
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strobe<='0';
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if we='0' then
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if we='0' then
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we_out<='1';
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we_out<='1';
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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dbus_cyc_o<=strobe;
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dbus_cyc_o<=strobe;
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dbus_stb_o<=strobe;
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dbus_stb_o<=strobe;
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dbus_we_o<=we;
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dbus_we_o<=we;
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sel_no_rmw_gen: if not RMW generate
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sel_no_rmw_gen: if not RMW generate
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dbus_sel_o<=sel;
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dbus_sel_o<=sel;
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end generate;
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end generate;
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sel_rmw_gen: if RMW generate
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sel_rmw_gen: if RMW generate
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dbus_sel_o<=(others=>'1');
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dbus_sel_o<=(others=>'1');
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end generate;
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end generate;
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selected_byte_gen: for i in selected_byte'range generate
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selected_byte(i)<=(dbus_dat_i(i) and sel(0)) or
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(dbus_dat_i(i+8) and sel(1)) or
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(dbus_dat_i(i+16) and sel(2)) or
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(dbus_dat_i(i+24) and sel(3));
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end generate;
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process (clk_i) is
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process (clk_i) is
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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if byte_mode='0' then
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dbus_rdata<=dbus_dat_i;
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rdata_o<=dbus_dat_i;
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else
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rdata_o(7 downto 0)<=selected_byte;
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for i in rdata_o'high downto 8 loop
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rdata_o(i)<=selected_byte(selected_byte'high) and sig;
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end loop;
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end if;
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end if;
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end if;
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end process;
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end process;
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selected_byte_gen: for i in selected_byte'range generate
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selected_byte(i)<=(dbus_rdata(i) and sel(0)) or
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(dbus_rdata(i+8) and sel(1)) or
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(dbus_rdata(i+16) and sel(2)) or
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(dbus_rdata(i+24) and sel(3));
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end generate;
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rdata_o<=dbus_rdata when byte_mode='0' else
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X"000000"&selected_byte when selected_byte(selected_byte'high)='0' or sig='0' else
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X"FFFFFF"&selected_byte;
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we_o<=we_out;
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we_o<=we_out;
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busy_o<=strobe or we_out;
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busy_o<=strobe or we_out;
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end architecture;
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end architecture;
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