URL https://opencores.org/ocsvn/lxp32/lxp32/trunk

Subversion Repositories lxp32

[/] [lxp32/] [trunk/] [rtl/] [lxp32_icache.vhd] - Diff between revs 2 and 6

Rev 2	Rev 6
Line 109...	Line 109...
`ram_we<=wb_stb and wbm_ack_i;`	`ram_we<=wb_stb and wbm_ack_i;`
`ram_re<=lli_re_i or miss;`	`ram_re<=lli_re_i or miss;`

`ram_inst: entity work.lxp32_ram256x32(rtl)`	`ram_inst: entity work.lxp32_ram256x32(rtl)`
`port map(`	`port map(`
`wclk_i=>clk_i,`	`clk_i=>clk_i,`

`we_i=>ram_we,`	`we_i=>ram_we,`
`waddr_i=>ram_waddr,`	`waddr_i=>ram_waddr,`
`wdata_i=>wbm_dat_i,`	`wdata_i=>wbm_dat_i,`

`rclk_i=>clk_i,`
`re_i=>ram_re,`	`re_i=>ram_re,`
`raddr_i=>ram_raddr,`	`raddr_i=>ram_raddr,`
`rdata_o=>lli_dat_o`	`rdata_o=>lli_dat_o`
`);`	`);`

Line 200...	Line 200...
`if rising_edge(clk_i) then`	`if rising_edge(clk_i) then`
`if rst_i='1' then`	`if rst_i='1' then`
`burst_cnt<=0;`	`burst_cnt<=0;`
`wb_stb<='0';`	`wb_stb<='0';`
`wrap_cnt<=0;`	`wrap_cnt<=0;`
	`wb_cti<=(others=>'-');`
	`burst1<='-';`
	`current_offset<=(others=>'-');`
	`start_offset<=(others=>'-');`
	`current_base<=(others=>'-');`
	`next_base<=(others=>'-');`
	`prev_base<=(others=>'-');`

	`-- To suppress numeric_std warnings`
	`-- synthesis translate_off`
	`current_offset<=(others=>'0');`
	`start_offset<=(others=>'0');`
	`current_base<=(others=>'0');`
	`next_base<=(others=>'0');`
	`prev_base<=(others=>'0');`
	`-- synthesis translate_on`
`else`	`else`
`if burst_cnt=0 and init='1' then`	`if burst_cnt=0 and init='1' then`
`if miss='1' and near_miss='0' then`	`if miss='1' and near_miss='0' then`
`wb_stb<='1';`	`wb_stb<='1';`
`wb_cti<="010";`	`wb_cti<="010";`