| Line 18... |
Line 18... |
clk_i: in std_logic;
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clk_i: in std_logic;
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rst_i: in std_logic;
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rst_i: in std_logic;
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irq_i: in std_logic_vector(7 downto 0);
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irq_i: in std_logic_vector(7 downto 0);
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interrupts_enabled_i: in std_logic_vector(7 downto 0);
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interrupts_blocked_i: in std_logic_vector(7 downto 0);
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interrupt_valid_o: out std_logic;
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interrupt_valid_o: out std_logic;
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interrupt_vector_o: out std_logic_vector(2 downto 0);
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interrupt_vector_o: out std_logic_vector(2 downto 0);
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interrupt_ready_i: in std_logic;
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interrupt_ready_i: in std_logic;
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interrupt_return_i: in std_logic
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interrupt_return_i: in std_logic;
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sp_waddr_i: in std_logic_vector(7 downto 0);
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sp_we_i: in std_logic;
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sp_wdata_i: in std_logic_vector(31 downto 0)
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);
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);
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end entity;
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end entity;
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|
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architecture rtl of lxp32_interrupt_mux is
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architecture rtl of lxp32_interrupt_mux is
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| Line 39... |
Line 40... |
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signal pending_interrupts: std_logic_vector(irq_i'range):=(others=>'0');
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signal pending_interrupts: std_logic_vector(irq_i'range):=(others=>'0');
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|
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signal interrupt_valid: std_logic:='0';
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signal interrupt_valid: std_logic:='0';
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|
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signal interrupts_enabled: std_logic_vector(7 downto 0):=(others=>'0');
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signal interrupts_blocked: std_logic_vector(7 downto 0):=(others=>'0');
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|
|
begin
|
begin
|
|
|
-- Note: "disabled" interrupts (i.e. for which interrupts_enabled_i(i)='0')
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-- Note: "disabled" interrupts (i.e. for which interrupts_enabled_i(i)='0')
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-- are ignored completely, meaning that the interrupt handler won't be
|
-- are ignored completely, meaning that the interrupt handler won't be
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-- called even if the interrupt is enabled later. Conversely, "blocked"
|
-- called even if the interrupt is enabled later. Conversely, "blocked"
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| Line 55... |
Line 59... |
if rst_i='1' then
|
if rst_i='1' then
|
irq_reg<=(others=>'0');
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irq_reg<=(others=>'0');
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pending_interrupts<=(others=>'0');
|
pending_interrupts<=(others=>'0');
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state<=Ready;
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state<=Ready;
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interrupt_valid<='0';
|
interrupt_valid<='0';
|
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interrupt_vector_o<=(others=>'-');
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else
|
else
|
irq_reg<=irq_i;
|
irq_reg<=irq_i;
|
|
|
pending_interrupts<=(pending_interrupts or
|
pending_interrupts<=(pending_interrupts or
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(irq_i and not irq_reg)) and
|
(irq_i and not irq_reg)) and
|
interrupts_enabled_i;
|
interrupts_enabled;
|
|
|
case state is
|
case state is
|
when Ready =>
|
when Ready =>
|
for i in pending_interrupts'reverse_range loop -- lower interrupts have priority
|
for i in pending_interrupts'reverse_range loop -- lower interrupts have priority
|
if pending_interrupts(i)='1' and interrupts_blocked_i(i)='0' then
|
if pending_interrupts(i)='1' and interrupts_blocked(i)='0' then
|
pending_interrupts(i)<='0';
|
pending_interrupts(i)<='0';
|
interrupt_valid<='1';
|
interrupt_valid<='1';
|
interrupt_vector_o<=std_logic_vector(to_unsigned(i,3));
|
interrupt_vector_o<=std_logic_vector(to_unsigned(i,3));
|
state<=Requested;
|
state<=Requested;
|
exit;
|
exit;
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| Line 89... |
Line 94... |
end if;
|
end if;
|
end process;
|
end process;
|
|
|
interrupt_valid_o<=interrupt_valid;
|
interrupt_valid_o<=interrupt_valid;
|
|
|
|
process (clk_i) is
|
|
begin
|
|
if rising_edge(clk_i) then
|
|
if rst_i='1' then
|
|
interrupts_enabled<=(others=>'0');
|
|
interrupts_blocked<=(others=>'0');
|
|
elsif sp_we_i='1' and sp_waddr_i=X"FC" then
|
|
interrupts_enabled<=sp_wdata_i(7 downto 0);
|
|
interrupts_blocked<=sp_wdata_i(15 downto 8);
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
end architecture;
|
end architecture;
|
|
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No newline at end of file
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No newline at end of file
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