---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- DSP multiplier
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-- DSP multiplier
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--
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--
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-- Part of the LXP32 CPU
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-- Part of the LXP32 CPU
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--
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--
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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--
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--
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-- This multiplier is designed for technologies that provide fast
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-- This multiplier is designed for technologies that provide fast
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-- 16x16 multipliers, including most modern FPGA families. One
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-- 16x16 multipliers, including most modern FPGA families. One
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-- multiplication takes 2 cycles.
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-- multiplication takes 2 cycles.
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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entity lxp32_mul_dsp is
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entity lxp32_mul_dsp is
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port(
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port(
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clk_i: in std_logic;
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clk_i: in std_logic;
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rst_i: in std_logic;
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rst_i: in std_logic;
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ce_i: in std_logic;
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ce_i: in std_logic;
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op1_i: in std_logic_vector(31 downto 0);
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op1_i: in std_logic_vector(31 downto 0);
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op2_i: in std_logic_vector(31 downto 0);
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op2_i: in std_logic_vector(31 downto 0);
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ce_o: out std_logic;
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ce_o: out std_logic;
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result_o: out std_logic_vector(31 downto 0)
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result_o: out std_logic_vector(31 downto 0)
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);
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);
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end entity;
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end entity;
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architecture rtl of lxp32_mul_dsp is
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architecture rtl of lxp32_mul_dsp is
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signal pp00: std_logic_vector(31 downto 0);
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signal pp00: std_logic_vector(31 downto 0);
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signal pp01: std_logic_vector(31 downto 0);
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signal pp01: std_logic_vector(31 downto 0);
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signal pp10: std_logic_vector(31 downto 0);
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signal pp10: std_logic_vector(31 downto 0);
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signal product: unsigned(31 downto 0);
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signal product: unsigned(31 downto 0);
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signal ceo: std_logic:='0';
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signal ceo: std_logic:='0';
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begin
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begin
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mul00_inst: entity work.lxp32_mul16x16
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mul00_inst: entity work.lxp32_mul16x16
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port map(
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port map(
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clk_i=>clk_i,
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clk_i=>clk_i,
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a_i=>op1_i(15 downto 0),
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a_i=>op1_i(15 downto 0),
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b_i=>op2_i(15 downto 0),
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b_i=>op2_i(15 downto 0),
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p_o=>pp00
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p_o=>pp00
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);
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);
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mul01_inst: entity work.lxp32_mul16x16
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mul01_inst: entity work.lxp32_mul16x16
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port map(
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port map(
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clk_i=>clk_i,
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clk_i=>clk_i,
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a_i=>op1_i(15 downto 0),
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a_i=>op1_i(15 downto 0),
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b_i=>op2_i(31 downto 16),
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b_i=>op2_i(31 downto 16),
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p_o=>pp01
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p_o=>pp01
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);
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);
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mul10_inst: entity work.lxp32_mul16x16
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mul10_inst: entity work.lxp32_mul16x16
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port map(
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port map(
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clk_i=>clk_i,
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clk_i=>clk_i,
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a_i=>op1_i(31 downto 16),
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a_i=>op1_i(31 downto 16),
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b_i=>op2_i(15 downto 0),
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b_i=>op2_i(15 downto 0),
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p_o=>pp10
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p_o=>pp10
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);
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);
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product(31 downto 16)<=unsigned(pp00(31 downto 16))+unsigned(pp01(15 downto 0))+unsigned(pp10(15 downto 0));
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product(31 downto 16)<=unsigned(pp00(31 downto 16))+unsigned(pp01(15 downto 0))+unsigned(pp10(15 downto 0));
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product(15 downto 0)<=unsigned(pp00(15 downto 0));
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product(15 downto 0)<=unsigned(pp00(15 downto 0));
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result_o<=std_logic_vector(product);
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result_o<=std_logic_vector(product);
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process (clk_i) is
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process (clk_i) is
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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if rst_i='1' then
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if rst_i='1' then
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ceo<='0';
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ceo<='0';
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else
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else
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ceo<=ce_i;
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ceo<=ce_i;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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ce_o<=ceo;
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ce_o<=ceo;
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end architecture;
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end architecture;
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