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[/] [lxp32/] [trunk/] [rtl/] [lxp32_mul_opt.vhd] - Diff between revs 2 and 6

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Rev 2 Rev 6
Line 63... Line 63...
signal acc_sum: unsigned(31 downto 0);
signal acc_sum: unsigned(31 downto 0);
signal acc_carry: unsigned(31 downto 0);
signal acc_carry: unsigned(31 downto 0);
 
 
signal cnt: integer range 0 to 4:=0;
signal cnt: integer range 0 to 4:=0;
 
 
 
signal result: std_logic_vector(result_o'range);
signal ceo: std_logic:='0';
signal ceo: std_logic:='0';
 
 
begin
begin
 
 
-- Calculate 8 partial products in parallel
-- Calculate 8 partial products in parallel
Line 107... Line 108...
begin
begin
        if rising_edge(clk_i) then
        if rising_edge(clk_i) then
                if rst_i='1' then
                if rst_i='1' then
                        ceo<='0';
                        ceo<='0';
                        cnt<=0;
                        cnt<=0;
 
                        reg1<=(others=>'-');
 
                        reg2<=(others=>'-');
 
                        acc_sum<=(others=>'-');
 
                        acc_carry<=(others=>'-');
 
                else
 
                        if cnt=1 then
 
                                ceo<='1';
                else
                else
                        ceo<='0';
                        ceo<='0';
 
                        end if;
 
 
                        if ce_i='1' then
                        if ce_i='1' then
                                cnt<=4;
                                cnt<=4;
                                reg1<=unsigned(op1_i);
                                reg1<=unsigned(op1_i);
                                reg2<=unsigned(op2_i);
                                reg2<=unsigned(op2_i);
                                acc_sum<=(others=>'0');
                                acc_sum<=(others=>'0');
                                acc_carry<=(others=>'0');
                                acc_carry<=(others=>'0');
                        elsif cnt>0 then
                        else
                                acc_sum<=pp_sum(7);
                                acc_sum<=pp_sum(7);
                                acc_carry<=pp_carry(7)(acc_carry'range);
                                acc_carry<=pp_carry(7)(acc_carry'range);
                                reg1<=reg1(reg1'high-8 downto 0)&X"00";
                                reg1<=reg1(reg1'high-8 downto 0)&X"00";
                                reg2<=X"00"&reg2(reg2'high downto 8);
                                reg2<=X"00"&reg2(reg2'high downto 8);
 
                                if cnt>0 then
                                cnt<=cnt-1;
                                cnt<=cnt-1;
                                if cnt=1 then
 
                                        ceo<='1';
 
                                end if;
                                end if;
                        end if;
                        end if;
                end if;
                end if;
        end if;
        end if;
end process;
end process;
 
 
result_o<=std_logic_vector(acc_sum+acc_carry);
result<=std_logic_vector(acc_sum+acc_carry);
 
 
 
result_o<=result;
ce_o<=ceo;
ce_o<=ceo;
 
 
 
-- A simulation-time multiplication check
 
 
 
-- synthesis translate_off
 
 
 
process (clk_i) is
 
        variable p: unsigned(op1_i'length+op2_i'length-1 downto 0);
 
begin
 
        if rising_edge(clk_i) then
 
                if ce_i='1' then
 
                        p:=unsigned(op1_i)*unsigned(op2_i);
 
                elsif ceo='1' then
 
                        assert result=std_logic_vector(p(result'range))
 
                                report "Incorrect multiplication result"
 
                                severity failure;
 
                end if;
 
        end if;
 
end process;
 
 
 
-- synthesis translate_on
 
 
end architecture;
end architecture;
 
 
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