---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- Sequential multiplier
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-- Sequential multiplier
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--
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--
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-- Part of the LXP32 CPU
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-- Part of the LXP32 CPU
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--
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--
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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--
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--
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-- The smallest possible multiplier. Implemented using
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-- The smallest possible multiplier. Implemented using
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-- an accumulator. One multiplication takes 34 cycles.
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-- an accumulator. One multiplication takes 34 cycles.
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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entity lxp32_mul_seq is
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entity lxp32_mul_seq is
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port(
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port(
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clk_i: in std_logic;
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clk_i: in std_logic;
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rst_i: in std_logic;
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rst_i: in std_logic;
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ce_i: in std_logic;
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ce_i: in std_logic;
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op1_i: in std_logic_vector(31 downto 0);
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op1_i: in std_logic_vector(31 downto 0);
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op2_i: in std_logic_vector(31 downto 0);
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op2_i: in std_logic_vector(31 downto 0);
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ce_o: out std_logic;
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ce_o: out std_logic;
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result_o: out std_logic_vector(31 downto 0)
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result_o: out std_logic_vector(31 downto 0)
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);
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);
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end entity;
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end entity;
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architecture rtl of lxp32_mul_seq is
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architecture rtl of lxp32_mul_seq is
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signal reg1: unsigned(op1_i'range);
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signal reg1: unsigned(op1_i'range);
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signal reg2: unsigned(op2_i'range);
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signal reg2: unsigned(op2_i'range);
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signal pp: unsigned(31 downto 0);
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signal pp: unsigned(31 downto 0);
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signal acc_sum: unsigned(31 downto 0);
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signal acc_sum: unsigned(31 downto 0);
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signal cnt: integer range 0 to 32:=0;
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signal cnt: integer range 0 to 32:=0;
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signal ceo: std_logic:='0';
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signal ceo: std_logic:='0';
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begin
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begin
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pp<=reg1 when reg2(0)='1' else (others=>'0');
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pp<=reg1 when reg2(0)='1' else (others=>'0');
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process (clk_i) is
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process (clk_i) is
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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if rst_i='1' then
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if rst_i='1' then
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ceo<='0';
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ceo<='0';
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cnt<=0;
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cnt<=0;
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reg1<=(others=>'-');
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reg1<=(others=>'-');
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reg2<=(others=>'-');
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reg2<=(others=>'-');
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acc_sum<=(others=>'-');
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acc_sum<=(others=>'-');
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else
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else
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if cnt=1 then
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if cnt=1 then
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ceo<='1';
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ceo<='1';
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else
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else
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ceo<='0';
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ceo<='0';
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end if;
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end if;
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if ce_i='1' then
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if ce_i='1' then
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cnt<=32;
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cnt<=32;
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reg1<=unsigned(op1_i);
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reg1<=unsigned(op1_i);
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reg2<=unsigned(op2_i);
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reg2<=unsigned(op2_i);
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acc_sum<=(others=>'0');
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acc_sum<=(others=>'0');
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else
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else
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acc_sum<=acc_sum+pp;
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acc_sum<=acc_sum+pp;
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reg1<=reg1(reg1'high-1 downto 0)&"0";
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reg1<=reg1(reg1'high-1 downto 0)&"0";
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reg2<="0"®2(reg2'high downto 1);
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reg2<="0"®2(reg2'high downto 1);
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if cnt>0 then
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if cnt>0 then
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cnt<=cnt-1;
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cnt<=cnt-1;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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result_o<=std_logic_vector(acc_sum);
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result_o<=std_logic_vector(acc_sum);
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ce_o<=ceo;
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ce_o<=ceo;
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end architecture;
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end architecture;
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