---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- Generic dual-port memory
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-- Generic dual-port memory
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--
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--
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-- Part of the LXP32 CPU
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-- Part of the LXP32 CPU
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--
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--
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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--
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--
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-- Portable description of a dual-port memory block with one write
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-- Portable description of a dual-port memory block with one write
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-- port. Major FPGA synthesis tools can infer on-chip block RAM
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-- port. Major FPGA synthesis tools can infer on-chip block RAM
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-- from this description. Can be replaced with a library component
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-- from this description. Can be replaced with a library component
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-- wrapper if needed.
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-- wrapper if needed.
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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entity lxp32_ram256x32 is
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entity lxp32_ram256x32 is
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port(
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port(
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clk_i: in std_logic;
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clk_i: in std_logic;
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we_i: in std_logic;
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we_i: in std_logic;
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waddr_i: in std_logic_vector(7 downto 0);
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waddr_i: in std_logic_vector(7 downto 0);
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wdata_i: in std_logic_vector(31 downto 0);
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wdata_i: in std_logic_vector(31 downto 0);
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re_i: in std_logic;
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re_i: in std_logic;
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raddr_i: in std_logic_vector(7 downto 0);
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raddr_i: in std_logic_vector(7 downto 0);
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rdata_o: out std_logic_vector(31 downto 0)
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rdata_o: out std_logic_vector(31 downto 0)
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);
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);
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end entity;
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end entity;
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architecture rtl of lxp32_ram256x32 is
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architecture rtl of lxp32_ram256x32 is
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type ram_type is array(255 downto 0) of std_logic_vector(31 downto 0);
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type ram_type is array(255 downto 0) of std_logic_vector(31 downto 0);
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signal ram: ram_type:=(others=>(others=>'0')); -- zero-initialize for SRAM-based FPGAs
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signal ram: ram_type:=(others=>(others=>'0')); -- zero-initialize for SRAM-based FPGAs
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attribute syn_ramstyle: string;
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attribute syn_ramstyle: string;
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attribute syn_ramstyle of ram: signal is "no_rw_check";
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attribute syn_ramstyle of ram: signal is "no_rw_check";
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attribute ram_style: string; -- for Xilinx
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attribute ram_style: string; -- for Xilinx
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attribute ram_style of ram: signal is "block";
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attribute ram_style of ram: signal is "block";
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begin
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begin
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-- Write port
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-- Write port
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process (clk_i) is
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process (clk_i) is
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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if we_i='1' then
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if we_i='1' then
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ram(to_integer(unsigned(waddr_i)))<=wdata_i;
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ram(to_integer(unsigned(waddr_i)))<=wdata_i;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- Read port
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-- Read port
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process (clk_i) is
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process (clk_i) is
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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if re_i='1' then
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if re_i='1' then
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if is_x(raddr_i) then -- to avoid numeric_std warnings during simulation
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if is_x(raddr_i) then -- to avoid numeric_std warnings during simulation
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rdata_o<=(others=>'X');
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rdata_o<=(others=>'X');
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else
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else
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rdata_o<=ram(to_integer(unsigned(raddr_i)));
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rdata_o<=ram(to_integer(unsigned(raddr_i)));
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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end architecture;
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end architecture;
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