---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- Scratchpad
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-- Scratchpad
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--
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--
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-- Part of the LXP32 CPU
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-- Part of the LXP32 CPU
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--
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--
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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--
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--
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-- LXP32 register file implemented as a RAM block. Since we need
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-- LXP32 register file implemented as a RAM block. Since we need
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-- to read two registers simultaneously, the memory is duplicated.
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-- to read two registers simultaneously, the memory is duplicated.
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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entity lxp32_scratchpad is
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entity lxp32_scratchpad is
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port(
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port(
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clk_i: in std_logic;
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clk_i: in std_logic;
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raddr1_i: in std_logic_vector(7 downto 0);
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raddr1_i: in std_logic_vector(7 downto 0);
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rdata1_o: out std_logic_vector(31 downto 0);
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rdata1_o: out std_logic_vector(31 downto 0);
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raddr2_i: in std_logic_vector(7 downto 0);
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raddr2_i: in std_logic_vector(7 downto 0);
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rdata2_o: out std_logic_vector(31 downto 0);
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rdata2_o: out std_logic_vector(31 downto 0);
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waddr_i: in std_logic_vector(7 downto 0);
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waddr_i: in std_logic_vector(7 downto 0);
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we_i: in std_logic;
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we_i: in std_logic;
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wdata_i: in std_logic_vector(31 downto 0)
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wdata_i: in std_logic_vector(31 downto 0)
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);
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);
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end entity;
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end entity;
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architecture rtl of lxp32_scratchpad is
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architecture rtl of lxp32_scratchpad is
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signal wdata_reg: std_logic_vector(wdata_i'range);
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signal wdata_reg: std_logic_vector(wdata_i'range);
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signal ram1_rdata: std_logic_vector(31 downto 0);
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signal ram1_rdata: std_logic_vector(31 downto 0);
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signal ram2_rdata: std_logic_vector(31 downto 0);
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signal ram2_rdata: std_logic_vector(31 downto 0);
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signal ram1_collision: std_logic;
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signal ram1_collision: std_logic;
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signal ram2_collision: std_logic;
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signal ram2_collision: std_logic;
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begin
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begin
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-- RAM 1
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-- RAM 1
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ram_inst1: entity work.lxp32_ram256x32(rtl)
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ram_inst1: entity work.lxp32_ram256x32(rtl)
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port map(
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port map(
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clk_i=>clk_i,
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clk_i=>clk_i,
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we_i=>we_i,
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we_i=>we_i,
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waddr_i=>waddr_i,
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waddr_i=>waddr_i,
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wdata_i=>wdata_i,
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wdata_i=>wdata_i,
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re_i=>'1',
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re_i=>'1',
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raddr_i=>raddr1_i,
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raddr_i=>raddr1_i,
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rdata_o=>ram1_rdata
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rdata_o=>ram1_rdata
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);
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);
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-- RAM 2
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-- RAM 2
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ram_inst2: entity work.lxp32_ram256x32(rtl)
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ram_inst2: entity work.lxp32_ram256x32(rtl)
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port map(
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port map(
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clk_i=>clk_i,
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clk_i=>clk_i,
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we_i=>we_i,
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we_i=>we_i,
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waddr_i=>waddr_i,
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waddr_i=>waddr_i,
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wdata_i=>wdata_i,
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wdata_i=>wdata_i,
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re_i=>'1',
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re_i=>'1',
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raddr_i=>raddr2_i,
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raddr_i=>raddr2_i,
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rdata_o=>ram2_rdata
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rdata_o=>ram2_rdata
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);
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);
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-- Read/write collision detection
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-- Read/write collision detection
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process (clk_i) is
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process (clk_i) is
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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wdata_reg<=wdata_i;
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wdata_reg<=wdata_i;
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if waddr_i=raddr1_i and we_i='1' then
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if waddr_i=raddr1_i and we_i='1' then
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ram1_collision<='1';
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ram1_collision<='1';
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else
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else
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ram1_collision<='0';
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ram1_collision<='0';
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end if;
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end if;
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if waddr_i=raddr2_i and we_i='1' then
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if waddr_i=raddr2_i and we_i='1' then
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ram2_collision<='1';
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ram2_collision<='1';
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else
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else
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ram2_collision<='0';
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ram2_collision<='0';
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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rdata1_o<=ram1_rdata when ram1_collision='0' else wdata_reg;
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rdata1_o<=ram1_rdata when ram1_collision='0' else wdata_reg;
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rdata2_o<=ram2_rdata when ram2_collision='0' else wdata_reg;
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rdata2_o<=ram2_rdata when ram2_collision='0' else wdata_reg;
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end architecture;
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end architecture;
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