---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- Barrel shifter
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-- Barrel shifter
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--
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--
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-- Part of the LXP32 CPU
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-- Part of the LXP32 CPU
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--
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--
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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--
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--
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-- Performs logical (unsigned) and arithmetic (signed) shifts
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-- Performs logical (unsigned) and arithmetic (signed) shifts
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-- in both directions. Pipeline latency: 1 cycle.
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-- in both directions. Pipeline latency: 1 cycle.
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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entity lxp32_shifter is
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entity lxp32_shifter is
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port(
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port(
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clk_i: in std_logic;
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clk_i: in std_logic;
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rst_i: in std_logic;
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rst_i: in std_logic;
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ce_i: in std_logic;
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ce_i: in std_logic;
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d_i: in std_logic_vector(31 downto 0);
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d_i: in std_logic_vector(31 downto 0);
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s_i: in std_logic_vector(4 downto 0);
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s_i: in std_logic_vector(4 downto 0);
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right_i: in std_logic;
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right_i: in std_logic;
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sig_i: in std_logic;
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sig_i: in std_logic;
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ce_o: out std_logic;
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ce_o: out std_logic;
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d_o: out std_logic_vector(31 downto 0)
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d_o: out std_logic_vector(31 downto 0)
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);
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);
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end entity;
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end entity;
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architecture rtl of lxp32_shifter is
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architecture rtl of lxp32_shifter is
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signal data: std_logic_vector(d_i'range);
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signal data: std_logic_vector(d_i'range);
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signal data_shifted: std_logic_vector(d_i'range);
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signal data_shifted: std_logic_vector(d_i'range);
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signal fill: std_logic; -- 0 for unsigned shifts, sign bit for signed ones
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signal fill: std_logic; -- 0 for unsigned shifts, sign bit for signed ones
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signal fill_v: std_logic_vector(3 downto 0);
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signal fill_v: std_logic_vector(3 downto 0);
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type cascades_type is array (4 downto 0) of std_logic_vector(d_i'range);
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type cascades_type is array (4 downto 0) of std_logic_vector(d_i'range);
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signal cascades: cascades_type;
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signal cascades: cascades_type;
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signal stage2_data: std_logic_vector(d_i'range);
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signal stage2_data: std_logic_vector(d_i'range);
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signal stage2_s: std_logic_vector(s_i'range);
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signal stage2_s: std_logic_vector(s_i'range);
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signal stage2_fill: std_logic;
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signal stage2_fill: std_logic;
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signal stage2_fill_v: std_logic_vector(15 downto 0);
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signal stage2_fill_v: std_logic_vector(15 downto 0);
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signal stage2_right: std_logic;
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signal stage2_right: std_logic;
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signal ceo: std_logic:='0';
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signal ceo: std_logic:='0';
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begin
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begin
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-- Internally, data are shifted in left direction. For right shifts
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-- Internally, data are shifted in left direction. For right shifts
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-- we reverse the argument's bit order
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-- we reverse the argument's bit order
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data_gen: for i in data'range generate
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data_gen: for i in data'range generate
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data(i)<=d_i(i) when right_i='0' else d_i(d_i'high-i);
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data(i)<=d_i(i) when right_i='0' else d_i(d_i'high-i);
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end generate;
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end generate;
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-- A set of cascaded shifters shifting by powers of two
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-- A set of cascaded shifters shifting by powers of two
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fill<=sig_i and data(0);
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fill<=sig_i and data(0);
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fill_v<=(others=>fill);
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fill_v<=(others=>fill);
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cascades(0)<=data(30 downto 0)&fill_v(0) when s_i(0)='1' else data;
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cascades(0)<=data(30 downto 0)&fill_v(0) when s_i(0)='1' else data;
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cascades(1)<=cascades(0)(29 downto 0)&fill_v(1 downto 0) when s_i(1)='1' else cascades(0);
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cascades(1)<=cascades(0)(29 downto 0)&fill_v(1 downto 0) when s_i(1)='1' else cascades(0);
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cascades(2)<=cascades(1)(27 downto 0)&fill_v(3 downto 0) when s_i(2)='1' else cascades(1);
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cascades(2)<=cascades(1)(27 downto 0)&fill_v(3 downto 0) when s_i(2)='1' else cascades(1);
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process (clk_i) is
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process (clk_i) is
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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if rst_i='1' then
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if rst_i='1' then
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ceo<='0';
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ceo<='0';
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stage2_data<=(others=>'-');
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stage2_data<=(others=>'-');
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stage2_s<=(others=>'-');
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stage2_s<=(others=>'-');
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stage2_fill<='-';
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stage2_fill<='-';
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stage2_right<='-';
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stage2_right<='-';
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else
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else
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ceo<=ce_i;
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ceo<=ce_i;
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stage2_data<=cascades(2);
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stage2_data<=cascades(2);
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stage2_s<=s_i;
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stage2_s<=s_i;
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stage2_fill<=fill;
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stage2_fill<=fill;
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stage2_right<=right_i;
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stage2_right<=right_i;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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stage2_fill_v<=(others=>stage2_fill);
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stage2_fill_v<=(others=>stage2_fill);
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cascades(3)<=stage2_data(23 downto 0)&stage2_fill_v(7 downto 0) when stage2_s(3)='1' else stage2_data;
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cascades(3)<=stage2_data(23 downto 0)&stage2_fill_v(7 downto 0) when stage2_s(3)='1' else stage2_data;
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cascades(4)<=cascades(3)(15 downto 0)&stage2_fill_v(15 downto 0) when stage2_s(4)='1' else cascades(3);
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cascades(4)<=cascades(3)(15 downto 0)&stage2_fill_v(15 downto 0) when stage2_s(4)='1' else cascades(3);
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-- Reverse bit order back, if needed
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-- Reverse bit order back, if needed
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data_shifted_gen: for i in data_shifted'range generate
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data_shifted_gen: for i in data_shifted'range generate
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data_shifted(i)<=cascades(4)(i) when stage2_right='0' else cascades(4)(cascades(4)'high-i);
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data_shifted(i)<=cascades(4)(i) when stage2_right='0' else cascades(4)(cascades(4)'high-i);
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end generate;
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end generate;
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d_o<=data_shifted;
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d_o<=data_shifted;
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ce_o<=ceo;
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ce_o<=ceo;
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end architecture;
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end architecture;
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