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[/] [lxp32/] [trunk/] [rtl/] [lxp32_ubuf.vhd] - Diff between revs 2 and 6
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Rev 6 |
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Line 40... |
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type regs_type is array (1 downto 0) of std_logic_vector(DATA_WIDTH-1 downto 0);
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type regs_type is array (1 downto 0) of std_logic_vector(DATA_WIDTH-1 downto 0);
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signal regs: regs_type;
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signal regs: regs_type;
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signal regs_mux: regs_type;
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signal regs_mux: regs_type;
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signal wpointer: std_logic_vector(2 downto 0):="001";
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begin
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begin
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we<=we_i and not full;
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we<=we_i and not full;
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re<=re_i and not empty;
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re<=re_i and not empty;
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process (clk_i) is
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process (clk_i) is
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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if rst_i='1' then
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if rst_i='1' then
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wpointer<="001";
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empty<='1';
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empty<='1';
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full<='0';
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full<='0';
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regs<=(others=>(others=>'-'));
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else
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else
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if re='0' then
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if re='0' then
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regs<=regs_mux;
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regs(0)<=regs_mux(0);
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else
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else
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regs(0)<=regs_mux(1);
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regs(0)<=regs_mux(1);
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end if;
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end if;
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regs(1)<=regs_mux(1);
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if we='1' and re='0' then
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if we='1' and re='0' then
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wpointer<=wpointer(1 downto 0)&"0";
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empty<='0';
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empty<='0';
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full<=wpointer(1);
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full<=not empty;
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elsif we='0' and re='1' then
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elsif we='0' and re='1' then
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wpointer<="0"&wpointer(2 downto 1);
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empty<=not full;
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empty<=wpointer(1);
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full<='0';
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full<='0';
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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mux: for i in regs_mux'range generate
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regs_mux(0)<=regs(0) when we='0' or empty='0' else d_i;
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regs_mux(i)<=regs(i) when we='0' or wpointer(i)='0' else d_i;
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regs_mux(1)<=regs(1) when we='0' or empty='1' else d_i;
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end generate;
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d_o<=regs(0);
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d_o<=regs(0);
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empty_o<=empty;
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empty_o<=empty;
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full_o<=full;
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full_o<=full;
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