---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- LXP32U CPU top-level module (U-series, without instruction cache)
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-- LXP32U CPU top-level module (U-series, without instruction cache)
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--
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--
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-- Part of the LXP32 CPU
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-- Part of the LXP32 CPU
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--
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--
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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--
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--
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-- This version uses a Low Latency Interface for the instruction bus
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-- This version uses a Low Latency Interface for the instruction bus
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-- (IBUS). It is designed for low-latency slaves such as on-chip
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-- (IBUS). It is designed for low-latency slaves such as on-chip
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-- RAM blocks.
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-- RAM blocks.
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--
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--
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-- Parameters:
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-- Parameters:
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-- DBUS_RMW: Use RMW cycle instead of SEL_O() signal
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-- DBUS_RMW: Use RMW cycle instead of SEL_O() signal
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-- for byte-granular access to data bus
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-- for byte-granular access to data bus
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-- DIVIDER_EN: enable divider
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-- DIVIDER_EN: enable divider
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-- MUL_ARCH: multiplier architecture ("dsp", "opt"
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-- MUL_ARCH: multiplier architecture ("dsp", "opt"
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-- or "seq")
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-- or "seq")
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-- START_ADDR: address in program memory where execution
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-- START_ADDR: address in program memory where execution
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-- starts
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-- starts
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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entity lxp32u_top is
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entity lxp32u_top is
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generic(
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generic(
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DBUS_RMW: boolean:=false;
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DBUS_RMW: boolean:=false;
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DIVIDER_EN: boolean:=true;
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DIVIDER_EN: boolean:=true;
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MUL_ARCH: string:="dsp";
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MUL_ARCH: string:="dsp";
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START_ADDR: std_logic_vector(31 downto 0):=(others=>'0')
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START_ADDR: std_logic_vector(31 downto 0):=(others=>'0')
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);
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);
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port(
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port(
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clk_i: in std_logic;
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clk_i: in std_logic;
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rst_i: in std_logic;
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rst_i: in std_logic;
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lli_re_o: out std_logic;
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lli_re_o: out std_logic;
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lli_adr_o: out std_logic_vector(29 downto 0);
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lli_adr_o: out std_logic_vector(29 downto 0);
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lli_dat_i: in std_logic_vector(31 downto 0);
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lli_dat_i: in std_logic_vector(31 downto 0);
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lli_busy_i: in std_logic;
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lli_busy_i: in std_logic;
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dbus_cyc_o: out std_logic;
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dbus_cyc_o: out std_logic;
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dbus_stb_o: out std_logic;
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dbus_stb_o: out std_logic;
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dbus_we_o: out std_logic;
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dbus_we_o: out std_logic;
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dbus_sel_o: out std_logic_vector(3 downto 0);
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dbus_sel_o: out std_logic_vector(3 downto 0);
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dbus_ack_i: in std_logic;
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dbus_ack_i: in std_logic;
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dbus_adr_o: out std_logic_vector(31 downto 2);
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dbus_adr_o: out std_logic_vector(31 downto 2);
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dbus_dat_o: out std_logic_vector(31 downto 0);
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dbus_dat_o: out std_logic_vector(31 downto 0);
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dbus_dat_i: in std_logic_vector(31 downto 0);
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dbus_dat_i: in std_logic_vector(31 downto 0);
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irq_i: in std_logic_vector(7 downto 0)
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irq_i: in std_logic_vector(7 downto 0)
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);
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);
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end entity;
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end entity;
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architecture rtl of lxp32u_top is
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architecture rtl of lxp32u_top is
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begin
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begin
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cpu_inst: entity work.lxp32_cpu(rtl)
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cpu_inst: entity work.lxp32_cpu(rtl)
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generic map(
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generic map(
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DBUS_RMW=>DBUS_RMW,
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DBUS_RMW=>DBUS_RMW,
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DIVIDER_EN=>DIVIDER_EN,
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DIVIDER_EN=>DIVIDER_EN,
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MUL_ARCH=>MUL_ARCH,
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MUL_ARCH=>MUL_ARCH,
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START_ADDR=>START_ADDR
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START_ADDR=>START_ADDR
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)
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)
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port map(
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port map(
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clk_i=>clk_i,
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clk_i=>clk_i,
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rst_i=>rst_i,
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rst_i=>rst_i,
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lli_re_o=>lli_re_o,
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lli_re_o=>lli_re_o,
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lli_adr_o=>lli_adr_o,
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lli_adr_o=>lli_adr_o,
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lli_dat_i=>lli_dat_i,
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lli_dat_i=>lli_dat_i,
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lli_busy_i=>lli_busy_i,
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lli_busy_i=>lli_busy_i,
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dbus_cyc_o=>dbus_cyc_o,
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dbus_cyc_o=>dbus_cyc_o,
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dbus_stb_o=>dbus_stb_o,
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dbus_stb_o=>dbus_stb_o,
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dbus_we_o=>dbus_we_o,
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dbus_we_o=>dbus_we_o,
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dbus_sel_o=>dbus_sel_o,
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dbus_sel_o=>dbus_sel_o,
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dbus_ack_i=>dbus_ack_i,
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dbus_ack_i=>dbus_ack_i,
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dbus_adr_o=>dbus_adr_o,
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dbus_adr_o=>dbus_adr_o,
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dbus_dat_o=>dbus_dat_o,
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dbus_dat_o=>dbus_dat_o,
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dbus_dat_i=>dbus_dat_i,
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dbus_dat_i=>dbus_dat_i,
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irq_i=>irq_i
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irq_i=>irq_i
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);
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);
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end architecture;
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end architecture;
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