| Line 43... |
Line 43... |
signal request: std_logic:='0';
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signal request: std_logic:='0';
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signal request_addr: std_logic_vector(29 downto 0);
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signal request_addr: std_logic_vector(29 downto 0);
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signal finish: std_logic:='0';
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signal finish: std_logic:='0';
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shared variable current_latency: integer:=1;
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signal current_latency: integer:=1;
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shared variable max_latency: integer:=-1;
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signal max_latency: integer:=-1;
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shared variable total_latency: integer:=0;
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signal total_latency: integer:=0;
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shared variable total_requests: integer:=0;
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signal spurious_misses: integer:=0;
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shared variable spurious_misses: integer:=0;
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begin
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begin
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process is
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process is
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variable b: integer:=1;
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variable b: integer:=1;
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variable start: integer;
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variable start: integer;
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variable size: integer;
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variable size: integer;
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variable addr: integer:=0;
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variable addr: integer:=0;
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variable delay: integer;
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variable delay: integer;
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variable rng_state: rng_state_type;
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variable r: integer;
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variable total_requests: integer:=0;
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begin
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begin
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while b<=BLOCKS loop
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while b<=BLOCKS loop
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if rand(1,10)=1 then -- insert large block occasionally
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rand(rng_state,1,10,r);
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size:=rand(1,400);
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if r=1 then -- insert large block occasionally
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rand(rng_state,1,400,size);
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else -- small block
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else -- small block
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size:=rand(1,32);
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rand(rng_state,1,32,size);
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end if;
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end if;
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if rand(0,1)=0 then -- long jump
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rand(rng_state,0,1,r);
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start:=rand(0,1024);
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if r=0 then -- long jump
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rand(rng_state,0,1024,start);
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addr:=start;
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addr:=start;
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if VERBOSE then
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if VERBOSE then
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report "Fetching block #"&integer'image(b)&" at address "&integer'image(addr)&
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report "Fetching block #"&integer'image(b)&" at address "&integer'image(addr)&
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" of size "&integer'image(size);
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" of size "&integer'image(size);
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end if;
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end if;
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else -- short jump
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else -- short jump
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start:=addr+rand(0,20)-10;
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rand(rng_state,-10,10,r);
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start:=addr+r;
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if start<0 then
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if start<0 then
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start:=0;
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start:=0;
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end if;
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end if;
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addr:=start;
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addr:=start;
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if VERBOSE then
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if VERBOSE then
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| Line 91... |
Line 96... |
total_requests:=total_requests+1;
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total_requests:=total_requests+1;
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lli_adr<=std_logic_vector(to_unsigned(addr,30));
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lli_adr<=std_logic_vector(to_unsigned(addr,30));
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wait until rising_edge(clk_i) and lli_busy_i='0';
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wait until rising_edge(clk_i) and lli_busy_i='0';
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re<='0';
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re<='0';
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addr:=addr+1;
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addr:=addr+1;
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delay:=rand(0,4);
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rand(rng_state,0,4,delay);
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if delay>0 then
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if delay>0 then
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for i in 1 to delay loop
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for i in 1 to delay loop
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wait until rising_edge(clk_i);
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wait until rising_edge(clk_i);
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end loop;
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end loop;
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end if;
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end if;
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Line 150... |
process (clk_i) is
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process (clk_i) is
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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if lli_busy_i='0' then
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if lli_busy_i='0' then
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if request='1' then
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if request='1' then
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total_latency:=total_latency+current_latency;
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total_latency<=total_latency+current_latency;
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if current_latency>max_latency then
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if current_latency>max_latency then
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max_latency:=current_latency;
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max_latency<=current_latency;
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end if;
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end if;
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end if;
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end if;
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current_latency:=1;
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current_latency<=1;
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else
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else
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if lli_dat_i=(("00"&request_addr) xor xor_constant) and current_latency=1 then
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if lli_dat_i=(("00"&request_addr) xor xor_constant) and current_latency=1 then
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spurious_misses:=spurious_misses+1;
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spurious_misses<=spurious_misses+1;
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end if;
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end if;
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current_latency:=current_latency+1;
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current_latency<=current_latency+1;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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assert not rising_edge(clk_i) or lli_busy_i='0' or request='1'
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process (clk_i) is
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begin
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if rising_edge(clk_i) then
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assert lli_busy_i='0' or request='1'
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report "LLI busy signal asserted without a request"
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report "LLI busy signal asserted without a request"
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severity failure;
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severity failure;
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end if;
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end process;
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end architecture;
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end architecture;
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No newline at end of file
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No newline at end of file
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