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[/] [lxp32/] [trunk/] [verify/] [icache/] [src/] [tb/] [ram_model.vhd] - Diff between revs 2 and 6

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Line 49... Line 49...
                end if;
                end if;
        end if;
        end if;
end process;
end process;
 
 
process is
process is
 
        variable rng_state: rng_state_type;
        variable delay: integer;
        variable delay: integer;
begin
begin
        wait until rising_edge(clk_i) and wbm_cyc_i='1' and wbm_stb_i='1';
        wait until rising_edge(clk_i) and wbm_cyc_i='1' and wbm_stb_i='1';
        ack<='0';
        ack<='0';
 
 
-- Random delay before the first beat
-- Random delay before the first beat
        if cycle='0' then
        if cycle='0' then
                delay:=rand(0,3);
                rand(rng_state,0,3,delay);
                if delay>0 then
                if delay>0 then
                        for i in 1 to delay loop
                        for i in 1 to delay loop
                                wait until rising_edge(clk_i) and wbm_cyc_i='1' and wbm_stb_i='1';
                                wait until rising_edge(clk_i) and wbm_cyc_i='1' and wbm_stb_i='1';
                        end loop;
                        end loop;
                end if;
                end if;

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