---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- RAM model
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-- RAM model
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--
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--
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-- Part of the LXP32 instruction cache testbench
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-- Part of the LXP32 instruction cache testbench
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--
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--
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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--
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--
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-- Simulates RAM controller which provides WISHBONE registered
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-- Simulates RAM controller which provides WISHBONE registered
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-- feedback interface.
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-- feedback interface.
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use work.common_pkg.all;
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use work.common_pkg.all;
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use work.tb_pkg.all;
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use work.tb_pkg.all;
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entity ram_model is
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entity ram_model is
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port(
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port(
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clk_i: in std_logic;
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clk_i: in std_logic;
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wbm_cyc_i: in std_logic;
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wbm_cyc_i: in std_logic;
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wbm_stb_i: in std_logic;
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wbm_stb_i: in std_logic;
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wbm_cti_i: in std_logic_vector(2 downto 0);
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wbm_cti_i: in std_logic_vector(2 downto 0);
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wbm_bte_i: in std_logic_vector(1 downto 0);
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wbm_bte_i: in std_logic_vector(1 downto 0);
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wbm_ack_o: out std_logic;
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wbm_ack_o: out std_logic;
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wbm_adr_i: in std_logic_vector(29 downto 0);
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wbm_adr_i: in std_logic_vector(29 downto 0);
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wbm_dat_o: out std_logic_vector(31 downto 0)
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wbm_dat_o: out std_logic_vector(31 downto 0)
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);
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);
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end entity;
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end entity;
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architecture sim of ram_model is
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architecture sim of ram_model is
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signal ack: std_logic:='0';
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signal ack: std_logic:='0';
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signal cycle: std_logic:='0';
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signal cycle: std_logic:='0';
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begin
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begin
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wbm_ack_o<=ack;
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wbm_ack_o<=ack;
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process (clk_i) is
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process (clk_i) is
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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if wbm_cyc_i='1' and wbm_stb_i='1' and wbm_cti_i="010" and wbm_bte_i="00" then
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if wbm_cyc_i='1' and wbm_stb_i='1' and wbm_cti_i="010" and wbm_bte_i="00" then
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cycle<='1';
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cycle<='1';
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elsif wbm_cyc_i='0' or (wbm_cyc_i='1' and wbm_stb_i='1' and (wbm_cti_i/="010" or wbm_bte_i/="00")) then
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elsif wbm_cyc_i='0' or (wbm_cyc_i='1' and wbm_stb_i='1' and (wbm_cti_i/="010" or wbm_bte_i/="00")) then
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cycle<='0';
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cycle<='0';
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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process is
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process is
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variable rng_state: rng_state_type;
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variable rng_state: rng_state_type;
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variable delay: integer;
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variable delay: integer;
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begin
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begin
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wait until rising_edge(clk_i) and wbm_cyc_i='1' and wbm_stb_i='1';
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wait until rising_edge(clk_i) and wbm_cyc_i='1' and wbm_stb_i='1';
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ack<='0';
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ack<='0';
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-- Random delay before the first beat
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-- Random delay before the first beat
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if cycle='0' then
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if cycle='0' then
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rand(rng_state,0,3,delay);
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rand(rng_state,0,3,delay);
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if delay>0 then
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if delay>0 then
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for i in 1 to delay loop
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for i in 1 to delay loop
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wait until rising_edge(clk_i) and wbm_cyc_i='1' and wbm_stb_i='1';
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wait until rising_edge(clk_i) and wbm_cyc_i='1' and wbm_stb_i='1';
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end loop;
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end loop;
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end if;
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end if;
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end if;
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end if;
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if ack='0' then
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if ack='0' then
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wbm_dat_o<=("00"&wbm_adr_i) xor xor_constant;
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wbm_dat_o<=("00"&wbm_adr_i) xor xor_constant;
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ack<='1';
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ack<='1';
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elsif wbm_cti_i="010" and wbm_bte_i="00" then
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elsif wbm_cti_i="010" and wbm_bte_i="00" then
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wbm_dat_o<=("00"&std_logic_vector(unsigned(wbm_adr_i)+1)) xor xor_constant;
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wbm_dat_o<=("00"&std_logic_vector(unsigned(wbm_adr_i)+1)) xor xor_constant;
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ack<='1';
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ack<='1';
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end if;
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end if;
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end process;
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end process;
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end architecture;
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end architecture;
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