---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- LXP32 instruction cache verification environment (self-checking
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-- LXP32 instruction cache verification environment (self-checking
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-- testbench)
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-- testbench)
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--
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--
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-- Part of the LXP32 instruction cache testbench
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-- Part of the LXP32 instruction cache testbench
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--
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--
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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--
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--
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-- Parameters:
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-- Parameters:
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-- CACHE_BURST_SIZE: burst size for cache unit
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-- CACHE_BURST_SIZE: burst size for cache unit
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-- CACHE_PREFETCH_SIZE: prefetch distance for cache unit
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-- CACHE_PREFETCH_SIZE: prefetch distance for cache unit
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-- CPU_BLOCKS: number of data blocks to fetch
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-- CPU_BLOCKS: number of data blocks to fetch
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-- VERBOSE: print more messages
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-- VERBOSE: print more messages
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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entity tb is
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entity tb is
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generic(
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generic(
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CACHE_BURST_SIZE: integer:=16;
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CACHE_BURST_SIZE: integer:=16;
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CACHE_PREFETCH_SIZE: integer:=32;
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CACHE_PREFETCH_SIZE: integer:=32;
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CPU_BLOCKS: integer:=100000;
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CPU_BLOCKS: integer:=100000;
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VERBOSE: boolean:=false
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VERBOSE: boolean:=false
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);
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);
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end entity;
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end entity;
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architecture testbench of tb is
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architecture testbench of tb is
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signal clk: std_logic:='0';
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signal clk: std_logic:='0';
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signal rst: std_logic:='0';
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signal rst: std_logic:='0';
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signal lli_re: std_logic;
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signal lli_re: std_logic;
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signal lli_adr: std_logic_vector(29 downto 0);
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signal lli_adr: std_logic_vector(29 downto 0);
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signal lli_dat: std_logic_vector(31 downto 0);
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signal lli_dat: std_logic_vector(31 downto 0);
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signal lli_busy: std_logic;
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signal lli_busy: std_logic;
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signal wbm_cyc: std_logic;
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signal wbm_cyc: std_logic;
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signal wbm_stb: std_logic;
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signal wbm_stb: std_logic;
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signal wbm_cti: std_logic_vector(2 downto 0);
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signal wbm_cti: std_logic_vector(2 downto 0);
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signal wbm_bte: std_logic_vector(1 downto 0);
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signal wbm_bte: std_logic_vector(1 downto 0);
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signal wbm_ack: std_logic;
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signal wbm_ack: std_logic;
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signal wbm_adr: std_logic_vector(29 downto 0);
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signal wbm_adr: std_logic_vector(29 downto 0);
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signal wbm_dat: std_logic_vector(31 downto 0);
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signal wbm_dat: std_logic_vector(31 downto 0);
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signal finish: std_logic:='0';
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signal finish: std_logic:='0';
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begin
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begin
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clk<=not clk and not finish after 5 ns;
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clk<=not clk and not finish after 5 ns;
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dut: entity work.lxp32_icache(rtl)
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dut: entity work.lxp32_icache(rtl)
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generic map(
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generic map(
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BURST_SIZE=>CACHE_BURST_SIZE,
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BURST_SIZE=>CACHE_BURST_SIZE,
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PREFETCH_SIZE=>CACHE_PREFETCH_SIZE
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PREFETCH_SIZE=>CACHE_PREFETCH_SIZE
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)
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)
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port map(
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port map(
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clk_i=>clk,
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clk_i=>clk,
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rst_i=>rst,
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rst_i=>rst,
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lli_re_i=>lli_re,
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lli_re_i=>lli_re,
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lli_adr_i=>lli_adr,
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lli_adr_i=>lli_adr,
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lli_dat_o=>lli_dat,
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lli_dat_o=>lli_dat,
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lli_busy_o=>lli_busy,
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lli_busy_o=>lli_busy,
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wbm_cyc_o=>wbm_cyc,
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wbm_cyc_o=>wbm_cyc,
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wbm_stb_o=>wbm_stb,
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wbm_stb_o=>wbm_stb,
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wbm_cti_o=>wbm_cti,
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wbm_cti_o=>wbm_cti,
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wbm_bte_o=>wbm_bte,
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wbm_bte_o=>wbm_bte,
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wbm_ack_i=>wbm_ack,
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wbm_ack_i=>wbm_ack,
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wbm_adr_o=>wbm_adr,
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wbm_adr_o=>wbm_adr,
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wbm_dat_i=>wbm_dat
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wbm_dat_i=>wbm_dat
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);
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);
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ram_model_inst: entity work.ram_model(sim)
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ram_model_inst: entity work.ram_model(sim)
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port map(
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port map(
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clk_i=>clk,
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clk_i=>clk,
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wbm_cyc_i=>wbm_cyc,
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wbm_cyc_i=>wbm_cyc,
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wbm_stb_i=>wbm_stb,
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wbm_stb_i=>wbm_stb,
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wbm_cti_i=>wbm_cti,
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wbm_cti_i=>wbm_cti,
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wbm_bte_i=>wbm_bte,
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wbm_bte_i=>wbm_bte,
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wbm_ack_o=>wbm_ack,
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wbm_ack_o=>wbm_ack,
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wbm_adr_i=>wbm_adr,
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wbm_adr_i=>wbm_adr,
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wbm_dat_o=>wbm_dat
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wbm_dat_o=>wbm_dat
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);
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);
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cpu_model_inst: entity work.cpu_model(sim)
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cpu_model_inst: entity work.cpu_model(sim)
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generic map(
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generic map(
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BLOCKS=>CPU_BLOCKS,
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BLOCKS=>CPU_BLOCKS,
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VERBOSE=>VERBOSE
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VERBOSE=>VERBOSE
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)
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)
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port map(
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port map(
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clk_i=>clk,
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clk_i=>clk,
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lli_re_o=>lli_re,
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lli_re_o=>lli_re,
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lli_adr_o=>lli_adr,
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lli_adr_o=>lli_adr,
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lli_dat_i=>lli_dat,
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lli_dat_i=>lli_dat,
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lli_busy_i=>lli_busy,
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lli_busy_i=>lli_busy,
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finish_o=>finish
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finish_o=>finish
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);
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);
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end architecture;
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end architecture;
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