URL https://opencores.org/ocsvn/lxp32/lxp32/trunk

Subversion Repositories lxp32

[/] [lxp32/] [trunk/] [verify/] [lxp32/] [src/] [firmware/] [test016.asm] - Diff between revs 9 and 12

Rev 9	Rev 12
Line 1...	Line 1...
`/*`	`/*`
`* Test for temporarily blocked interrupts`	`* Test wake-up interrupts`
`*/`	`*/`

`lc r100, 0x10000000 // test result output pointer`	`lc r100, 0x10000000 // test result output pointer`
`lc r101, halt`	`lc r101, halt`
`lc r102, failure`	`lc r102, 0x30000000 // coprocessor input register`
`lc r103, 0x20000000 // timer: number of pulses (0xFFFFFFFF - infinite)`	`lc r103, 0x30000004 // coprocessor output register`
`lc r104, 0x20000004 // timer: delay between pulses (in cycles)`	`lc r104, failure`

`lc iv0, timer_handler`
`lc cr, 0x101 // enable interrupt 0 in temporarily blocked state`

`lc r32, 0 // interrupt handler call counter`
`lc r33, 1000 // loop counter`
`lc r34, loop1`
`lc r35, loop2`

`sw r104, 100`
`sw r103, 1`

`loop1:`
`sub r33, r33, 1`
`cjmpug r34, r33, 0 // loop1`

`lc r33, 1000`
`mov cr, 1 // unblock interrupt 0`

`loop2:`
`sub r33, r33, 1`
`cjmpug r35, r33, 0 // loop2`

`// r32 should be 1 by this point`
`cjmpne r102, r32, 1 // failure`
`sw r100, 1`
`jmp r101 // halt`

`failure:`	`lcs cr, 0x0404 // enable coprocessor interrupt and mark it as wake-up`
`sw r100, 2`
	`sw r102, 33`

	`hlt`

	`lw r1, r103`
	`cjmpne r104, r1, 99`

	`sw r100, 1 // success`

`halt:`	`halt:`
`hlt`	`hlt`
`jmp r101 // halt`	`jmp r101 // halt`

`timer_handler:`	`failure:`
`add r32, r32, 1`	`sw r100, 2`
`iret`	`jmp r101 // halt`
`jmp r101 // halt`	`jmp r101 // halt`