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architecture rtl of dbus_monitor is
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architecture rtl of dbus_monitor is
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signal prbs: std_logic;
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signal prbs: std_logic;
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signal cycle: std_logic:='0';
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signal cycle: std_logic:='0';
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signal cyc_ff: std_logic:='0';
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signal ack_ff: std_logic:='0';
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begin
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begin
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-- Manage throttling
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-- Manage throttling
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gen_throttling: if THROTTLE generate
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gen_throttling: if THROTTLE generate
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wbm_we_o<=wbs_we_i;
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wbm_we_o<=wbs_we_i;
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wbm_sel_o<=wbs_sel_i;
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wbm_sel_o<=wbs_sel_i;
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wbm_adr_o<=wbs_adr_i;
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wbm_adr_o<=wbs_adr_i;
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wbm_dat_o<=wbs_dat_i;
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wbm_dat_o<=wbs_dat_i;
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assert not rising_edge(clk_i) or wbm_ack_i='0' or (wbs_cyc_i and (not prbs or cycle))='1'
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-- Check handshake correctness
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process (clk_i) is
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begin
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if rising_edge(clk_i) then
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if rst_i='1' then
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cyc_ff<='0';
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ack_ff<='0';
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else
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cyc_ff<=wbs_cyc_i;
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ack_ff<=wbm_ack_i;
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assert wbm_ack_i='0' or (wbs_cyc_i and (not prbs or cycle))='1'
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report "DBUS error: ACK asserted without CYC"
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report "DBUS error: ACK asserted without CYC"
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severity failure;
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severity failure;
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assert not (wbs_cyc_i='0' and cyc_ff='1' and ack_ff/='1')
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report "DBUS error: cycle terminated prematurely"
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severity failure;
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end if;
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end if;
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end process;
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end architecture;
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end architecture;
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