---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- DBUS monitor
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-- DBUS monitor
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--
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--
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-- Part of the LXP32 test platform
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-- Part of the LXP32 test platform
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--
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--
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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--
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--
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-- Monitors LXP32 data bus transactions, optionally throttles them.
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-- Monitors LXP32 data bus transactions, optionally throttles them.
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--
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--
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-- Note: regardless of whether this description is synthesizable,
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-- Note: regardless of whether this description is synthesizable,
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-- it was designed exclusively for simulation purposes.
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-- it was designed exclusively for simulation purposes.
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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entity dbus_monitor is
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entity dbus_monitor is
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generic(
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generic(
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THROTTLE: boolean
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THROTTLE: boolean
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);
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);
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port(
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port(
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clk_i: in std_logic;
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clk_i: in std_logic;
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rst_i: in std_logic;
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rst_i: in std_logic;
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wbs_cyc_i: in std_logic;
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wbs_cyc_i: in std_logic;
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wbs_stb_i: in std_logic;
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wbs_stb_i: in std_logic;
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wbs_we_i: in std_logic;
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wbs_we_i: in std_logic;
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wbs_sel_i: in std_logic_vector(3 downto 0);
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wbs_sel_i: in std_logic_vector(3 downto 0);
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wbs_ack_o: out std_logic;
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wbs_ack_o: out std_logic;
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wbs_adr_i: in std_logic_vector(31 downto 2);
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wbs_adr_i: in std_logic_vector(31 downto 2);
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wbs_dat_i: in std_logic_vector(31 downto 0);
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wbs_dat_i: in std_logic_vector(31 downto 0);
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wbs_dat_o: out std_logic_vector(31 downto 0);
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wbs_dat_o: out std_logic_vector(31 downto 0);
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wbm_cyc_o: out std_logic;
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wbm_cyc_o: out std_logic;
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wbm_stb_o: out std_logic;
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wbm_stb_o: out std_logic;
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wbm_we_o: out std_logic;
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wbm_we_o: out std_logic;
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wbm_sel_o: out std_logic_vector(3 downto 0);
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wbm_sel_o: out std_logic_vector(3 downto 0);
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wbm_ack_i: in std_logic;
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wbm_ack_i: in std_logic;
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wbm_adr_o: out std_logic_vector(31 downto 2);
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wbm_adr_o: out std_logic_vector(31 downto 2);
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wbm_dat_o: out std_logic_vector(31 downto 0);
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wbm_dat_o: out std_logic_vector(31 downto 0);
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wbm_dat_i: in std_logic_vector(31 downto 0)
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wbm_dat_i: in std_logic_vector(31 downto 0)
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);
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);
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end entity;
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end entity;
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architecture rtl of dbus_monitor is
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architecture rtl of dbus_monitor is
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signal prbs: std_logic;
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signal prbs: std_logic;
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signal cycle: std_logic:='0';
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signal cycle: std_logic:='0';
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signal cyc_ff: std_logic:='0';
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signal ack_ff: std_logic:='0';
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begin
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begin
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-- Manage throttling
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-- Manage throttling
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gen_throttling: if THROTTLE generate
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gen_throttling: if THROTTLE generate
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throttle_inst: entity work.scrambler(rtl)
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throttle_inst: entity work.scrambler(rtl)
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generic map(TAP1=>6,TAP2=>7)
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generic map(TAP1=>6,TAP2=>7)
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port map(clk_i=>clk_i,rst_i=>rst_i,ce_i=>'1',d_o=>prbs);
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port map(clk_i=>clk_i,rst_i=>rst_i,ce_i=>'1',d_o=>prbs);
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end generate;
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end generate;
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gen_no_throttling: if not THROTTLE generate
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gen_no_throttling: if not THROTTLE generate
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prbs<='0';
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prbs<='0';
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end generate;
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end generate;
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-- CPU interface
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-- CPU interface
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wbs_ack_o<=wbm_ack_i;
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wbs_ack_o<=wbm_ack_i;
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wbs_dat_o<=wbm_dat_i when wbm_ack_i='1' else (others=>'-');
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wbs_dat_o<=wbm_dat_i when wbm_ack_i='1' else (others=>'-');
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-- Interconnect interface
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-- Interconnect interface
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process (clk_i) is
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process (clk_i) is
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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if rst_i='1' then
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if rst_i='1' then
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cycle<='0';
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cycle<='0';
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elsif prbs='0' and wbs_cyc_i='1' then
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elsif prbs='0' and wbs_cyc_i='1' then
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cycle<='1';
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cycle<='1';
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elsif wbs_cyc_i='0' then
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elsif wbs_cyc_i='0' then
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cycle<='0';
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cycle<='0';
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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wbm_cyc_o<=wbs_cyc_i and (not prbs or cycle);
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wbm_cyc_o<=wbs_cyc_i and (not prbs or cycle);
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wbm_stb_o<=wbs_stb_i and (not prbs or cycle);
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wbm_stb_o<=wbs_stb_i and (not prbs or cycle);
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wbm_we_o<=wbs_we_i;
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wbm_we_o<=wbs_we_i;
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wbm_sel_o<=wbs_sel_i;
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wbm_sel_o<=wbs_sel_i;
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wbm_adr_o<=wbs_adr_i;
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wbm_adr_o<=wbs_adr_i;
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wbm_dat_o<=wbs_dat_i;
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wbm_dat_o<=wbs_dat_i;
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assert not rising_edge(clk_i) or wbm_ack_i='0' or (wbs_cyc_i and (not prbs or cycle))='1'
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-- Check handshake correctness
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process (clk_i) is
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begin
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if rising_edge(clk_i) then
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if rst_i='1' then
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cyc_ff<='0';
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ack_ff<='0';
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else
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cyc_ff<=wbs_cyc_i;
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ack_ff<=wbm_ack_i;
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assert wbm_ack_i='0' or (wbs_cyc_i and (not prbs or cycle))='1'
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report "DBUS error: ACK asserted without CYC"
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report "DBUS error: ACK asserted without CYC"
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severity failure;
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severity failure;
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assert not (wbs_cyc_i='0' and cyc_ff='1' and ack_ff/='1')
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report "DBUS error: cycle terminated prematurely"
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severity failure;
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end if;
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end if;
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end process;
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end architecture;
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end architecture;
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