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[/] [lxp32/] [trunk/] [verify/] [lxp32/] [src/] [platform/] [generic_dpram.vhd] - Diff between revs 2 and 6

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Rev 2	Rev 6
Line 47...	Line 47...

`type ram_type is array(SIZE-1 downto 0) of std_logic_vector(DATA_WIDTH-1 downto 0);`	`type ram_type is array(SIZE-1 downto 0) of std_logic_vector(DATA_WIDTH-1 downto 0);`
`signal ram: ram_type;`	`signal ram: ram_type;`

`attribute syn_ramstyle: string;`	`attribute syn_ramstyle: string;`
`attribute syn_ramstyle of ram: signal is "block_ram,no_rw_check";`	`attribute syn_ramstyle of ram: signal is "no_rw_check";`
`attribute ram_style: string; -- for Xilinx`	`attribute ram_style: string; -- for Xilinx`
`attribute ram_style of ram: signal is "block";`	`attribute ram_style of ram: signal is "block";`

`begin`	`begin`

Line 74...	Line 74...
`if cea_i='1' then`	`if cea_i='1' then`
`if wea_i='1' then`	`if wea_i='1' then`
`ram(to_integer(unsigned(addra_i)))<=da_i;`	`ram(to_integer(unsigned(addra_i)))<=da_i;`
`da_o<=(others=>'-');`	`da_o<=(others=>'-');`
`else`	`else`
`da_o<=ram(to_integer(to_01(unsigned(addra_i))));`	`if is_x(addra_i) then`
	`da_o<=(others=>'X');`
	`else`
	`da_o<=ram(to_integer(unsigned(addra_i)));`
	`end if;`
`end if;`	`end if;`
`end if;`	`end if;`
`end if;`	`end if;`
`end process;`	`end process;`
`end generate;`	`end generate;`
Line 90...	Line 94...
`if cea_i='1' then`	`if cea_i='1' then`
`if wea_i='1' then`	`if wea_i='1' then`
`ram(to_integer(unsigned(addra_i)))<=da_i;`	`ram(to_integer(unsigned(addra_i)))<=da_i;`
`da_o<=da_i;`	`da_o<=da_i;`
`else`	`else`
`da_o<=ram(to_integer(to_01(unsigned(addra_i))));`	`if is_x(addra_i) then`
	`da_o<=(others=>'X');`
	`else`
	`da_o<=ram(to_integer(unsigned(addra_i)));`
	`end if;`
`end if;`	`end if;`
`end if;`	`end if;`
`end if;`	`end if;`
`end process;`	`end process;`
`end generate;`	`end generate;`
Line 105...	Line 113...
`if rising_edge(clka_i) then`	`if rising_edge(clka_i) then`
`if cea_i='1' then`	`if cea_i='1' then`
`if wea_i='1' then`	`if wea_i='1' then`
`ram(to_integer(unsigned(addra_i)))<=da_i;`	`ram(to_integer(unsigned(addra_i)))<=da_i;`
`end if;`	`end if;`
`da_o<=ram(to_integer(to_01(unsigned(addra_i))));`	`if is_x(addra_i) then`
	`da_o<=(others=>'X');`
	`else`
	`da_o<=ram(to_integer(unsigned(addra_i)));`
	`end if;`
`end if;`	`end if;`
`end if;`	`end if;`
`end process;`	`end process;`
`end generate;`	`end generate;`

Line 119...	Line 131...
`if rising_edge(clka_i) then`	`if rising_edge(clka_i) then`
`if cea_i='1' then`	`if cea_i='1' then`
`if wea_i='1' then`	`if wea_i='1' then`
`ram(to_integer(unsigned(addra_i)))<=da_i;`	`ram(to_integer(unsigned(addra_i)))<=da_i;`
`else`	`else`
`da_o<=ram(to_integer(to_01(unsigned(addra_i))));`	`if is_x(addra_i) then`
	`da_o<=(others=>'X');`
	`else`
	`da_o<=ram(to_integer(unsigned(addra_i)));`
	`end if;`
`end if;`	`end if;`
`end if;`	`end if;`
`end if;`	`end if;`
`end process;`	`end process;`
`end generate;`	`end generate;`
Line 132...	Line 148...

`process (clkb_i) is`	`process (clkb_i) is`
`begin`	`begin`
`if rising_edge(clkb_i) then`	`if rising_edge(clkb_i) then`
`if ceb_i='1' then`	`if ceb_i='1' then`
`db_o<=ram(to_integer(to_01(unsigned(addrb_i))));`	`if is_x(addrb_i) then`
	`db_o<=(others=>'X');`
	`else`
	`db_o<=ram(to_integer(unsigned(addrb_i)));`
	`end if;`
`end if;`	`end if;`
`end if;`	`end if;`
`end process;`	`end process;`

`end architecture;`	`end architecture;`

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[/] [lxp32/] [trunk/] [verify/] [lxp32/] [src/] [platform/] [generic_dpram.vhd] - Diff between revs 2 and 6