---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- LXP32 platform top-level design unit
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-- LXP32 platform top-level design unit
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--
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--
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-- Part of the LXP32 test platform
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-- Part of the LXP32 test platform
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--
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--
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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--
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--
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-- A SoC-like simulation platform for the LXP32 CPU, containing
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-- A SoC-like simulation platform for the LXP32 CPU, containing
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-- a few peripherals such as program RAM, timer and coprocessor.
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-- a few peripherals such as program RAM, timer and coprocessor.
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--
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--
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-- Note: regardless of whether this description is synthesizable,
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-- Note: regardless of whether this description is synthesizable,
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-- it was designed exclusively for simulation purposes.
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-- it was designed exclusively for simulation purposes.
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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|
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entity platform is
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entity platform is
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generic(
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generic(
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CPU_DBUS_RMW: boolean;
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CPU_DBUS_RMW: boolean;
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CPU_MUL_ARCH: string;
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CPU_MUL_ARCH: string;
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MODEL_LXP32C: boolean;
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MODEL_LXP32C: boolean;
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THROTTLE_DBUS: boolean;
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THROTTLE_DBUS: boolean;
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THROTTLE_IBUS: boolean
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THROTTLE_IBUS: boolean
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);
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);
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port(
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port(
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clk_i: in std_logic;
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clk_i: in std_logic;
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rst_i: in std_logic;
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rst_i: in std_logic;
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cpu_rst_i: in std_logic;
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cpu_rst_i: in std_logic;
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|
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wbm_cyc_o: out std_logic;
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wbm_cyc_o: out std_logic;
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wbm_stb_o: out std_logic;
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wbm_stb_o: out std_logic;
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wbm_we_o: out std_logic;
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wbm_we_o: out std_logic;
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wbm_sel_o: out std_logic_vector(3 downto 0);
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wbm_sel_o: out std_logic_vector(3 downto 0);
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wbm_ack_i: in std_logic;
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wbm_ack_i: in std_logic;
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wbm_adr_o: out std_logic_vector(27 downto 2);
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wbm_adr_o: out std_logic_vector(27 downto 2);
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wbm_dat_o: out std_logic_vector(31 downto 0);
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wbm_dat_o: out std_logic_vector(31 downto 0);
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wbm_dat_i: in std_logic_vector(31 downto 0);
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wbm_dat_i: in std_logic_vector(31 downto 0);
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|
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wbs_cyc_i: in std_logic;
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wbs_cyc_i: in std_logic;
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wbs_stb_i: in std_logic;
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wbs_stb_i: in std_logic;
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wbs_we_i: in std_logic;
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wbs_we_i: in std_logic;
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wbs_sel_i: in std_logic_vector(3 downto 0);
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wbs_sel_i: in std_logic_vector(3 downto 0);
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wbs_ack_o: out std_logic;
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wbs_ack_o: out std_logic;
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wbs_adr_i: in std_logic_vector(31 downto 2);
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wbs_adr_i: in std_logic_vector(31 downto 2);
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wbs_dat_i: in std_logic_vector(31 downto 0);
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wbs_dat_i: in std_logic_vector(31 downto 0);
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wbs_dat_o: out std_logic_vector(31 downto 0);
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wbs_dat_o: out std_logic_vector(31 downto 0);
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|
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gp_io: inout std_logic_vector(31 downto 0)
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gp_io: inout std_logic_vector(31 downto 0)
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);
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);
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end entity;
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end entity;
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architecture rtl of platform is
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architecture rtl of platform is
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|
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type wbm_type is record
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type wbm_type is record
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cyc: std_logic;
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cyc: std_logic;
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stb: std_logic;
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stb: std_logic;
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we: std_logic;
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we: std_logic;
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sel: std_logic_vector(3 downto 0);
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sel: std_logic_vector(3 downto 0);
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ack: std_logic;
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ack: std_logic;
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adr: std_logic_vector(31 downto 2);
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adr: std_logic_vector(31 downto 2);
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wdata: std_logic_vector(31 downto 0);
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wdata: std_logic_vector(31 downto 0);
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rdata: std_logic_vector(31 downto 0);
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rdata: std_logic_vector(31 downto 0);
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end record;
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end record;
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type wbs_type is record
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type wbs_type is record
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cyc: std_logic;
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cyc: std_logic;
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stb: std_logic;
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stb: std_logic;
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we: std_logic;
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we: std_logic;
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sel: std_logic_vector(3 downto 0);
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sel: std_logic_vector(3 downto 0);
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ack: std_logic;
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ack: std_logic;
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adr: std_logic_vector(27 downto 2);
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adr: std_logic_vector(27 downto 2);
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wdata: std_logic_vector(31 downto 0);
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wdata: std_logic_vector(31 downto 0);
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rdata: std_logic_vector(31 downto 0);
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rdata: std_logic_vector(31 downto 0);
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end record;
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end record;
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type ibus_type is record
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type ibus_type is record
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cyc: std_logic;
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cyc: std_logic;
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stb: std_logic;
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stb: std_logic;
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cti: std_logic_vector(2 downto 0);
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cti: std_logic_vector(2 downto 0);
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bte: std_logic_vector(1 downto 0);
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bte: std_logic_vector(1 downto 0);
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ack: std_logic;
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ack: std_logic;
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adr: std_logic_vector(29 downto 0);
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adr: std_logic_vector(29 downto 0);
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dat: std_logic_vector(31 downto 0);
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dat: std_logic_vector(31 downto 0);
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end record;
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end record;
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|
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signal cpu_rst: std_logic;
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signal cpu_rst: std_logic;
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signal cpu_irq: std_logic_vector(7 downto 0);
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signal cpu_irq: std_logic_vector(7 downto 0);
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signal cpu_dbus: wbm_type;
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signal cpu_dbus: wbm_type;
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signal cpu_ibus: ibus_type;
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signal cpu_ibus: ibus_type;
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signal lli_re: std_logic;
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signal lli_re: std_logic;
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signal lli_adr: std_logic_vector(29 downto 0);
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signal lli_adr: std_logic_vector(29 downto 0);
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signal lli_dat: std_logic_vector(31 downto 0);
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signal lli_dat: std_logic_vector(31 downto 0);
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signal lli_busy: std_logic;
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signal lli_busy: std_logic;
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signal monitor_dbus: wbm_type;
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signal monitor_dbus: wbm_type;
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signal ram_wb: wbs_type;
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signal ram_wb: wbs_type;
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signal timer_wb: wbs_type;
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signal timer_wb: wbs_type;
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signal timer_elapsed: std_logic;
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signal timer_elapsed: std_logic;
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signal coprocessor_wb: wbs_type;
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signal coprocessor_wb: wbs_type;
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signal coprocessor_irq: std_logic;
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signal coprocessor_irq: std_logic;
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begin
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begin
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-- Interconnect
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-- Interconnect
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intercon_inst: entity work.intercon(rtl)
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intercon_inst: entity work.intercon(rtl)
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port map(
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port map(
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clk_i=>clk_i,
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clk_i=>clk_i,
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rst_i=>rst_i,
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rst_i=>rst_i,
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s0_cyc_i=>wbs_cyc_i,
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s0_cyc_i=>wbs_cyc_i,
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s0_stb_i=>wbs_stb_i,
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s0_stb_i=>wbs_stb_i,
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s0_we_i=>wbs_we_i,
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s0_we_i=>wbs_we_i,
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s0_sel_i=>wbs_sel_i,
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s0_sel_i=>wbs_sel_i,
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s0_ack_o=>wbs_ack_o,
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s0_ack_o=>wbs_ack_o,
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s0_adr_i=>wbs_adr_i,
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s0_adr_i=>wbs_adr_i,
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s0_dat_i=>wbs_dat_i,
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s0_dat_i=>wbs_dat_i,
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s0_dat_o=>wbs_dat_o,
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s0_dat_o=>wbs_dat_o,
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|
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s1_cyc_i=>monitor_dbus.cyc,
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s1_cyc_i=>monitor_dbus.cyc,
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s1_stb_i=>monitor_dbus.stb,
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s1_stb_i=>monitor_dbus.stb,
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s1_we_i=>monitor_dbus.we,
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s1_we_i=>monitor_dbus.we,
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s1_sel_i=>monitor_dbus.sel,
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s1_sel_i=>monitor_dbus.sel,
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s1_ack_o=>monitor_dbus.ack,
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s1_ack_o=>monitor_dbus.ack,
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s1_adr_i=>monitor_dbus.adr,
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s1_adr_i=>monitor_dbus.adr,
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s1_dat_i=>monitor_dbus.wdata,
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s1_dat_i=>monitor_dbus.wdata,
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s1_dat_o=>monitor_dbus.rdata,
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s1_dat_o=>monitor_dbus.rdata,
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|
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m0_cyc_o=>ram_wb.cyc,
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m0_cyc_o=>ram_wb.cyc,
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m0_stb_o=>ram_wb.stb,
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m0_stb_o=>ram_wb.stb,
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m0_we_o=>ram_wb.we,
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m0_we_o=>ram_wb.we,
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m0_sel_o=>ram_wb.sel,
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m0_sel_o=>ram_wb.sel,
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m0_ack_i=>ram_wb.ack,
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m0_ack_i=>ram_wb.ack,
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m0_adr_o=>ram_wb.adr,
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m0_adr_o=>ram_wb.adr,
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m0_dat_o=>ram_wb.wdata,
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m0_dat_o=>ram_wb.wdata,
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m0_dat_i=>ram_wb.rdata,
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m0_dat_i=>ram_wb.rdata,
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|
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m1_cyc_o=>wbm_cyc_o,
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m1_cyc_o=>wbm_cyc_o,
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m1_stb_o=>wbm_stb_o,
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m1_stb_o=>wbm_stb_o,
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m1_we_o=>wbm_we_o,
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m1_we_o=>wbm_we_o,
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m1_sel_o=>wbm_sel_o,
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m1_sel_o=>wbm_sel_o,
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m1_ack_i=>wbm_ack_i,
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m1_ack_i=>wbm_ack_i,
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m1_adr_o=>wbm_adr_o,
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m1_adr_o=>wbm_adr_o,
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m1_dat_o=>wbm_dat_o,
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m1_dat_o=>wbm_dat_o,
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m1_dat_i=>wbm_dat_i,
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m1_dat_i=>wbm_dat_i,
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|
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m2_cyc_o=>timer_wb.cyc,
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m2_cyc_o=>timer_wb.cyc,
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m2_stb_o=>timer_wb.stb,
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m2_stb_o=>timer_wb.stb,
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m2_we_o=>timer_wb.we,
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m2_we_o=>timer_wb.we,
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m2_sel_o=>timer_wb.sel,
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m2_sel_o=>timer_wb.sel,
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m2_ack_i=>timer_wb.ack,
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m2_ack_i=>timer_wb.ack,
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m2_adr_o=>timer_wb.adr,
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m2_adr_o=>timer_wb.adr,
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m2_dat_o=>timer_wb.wdata,
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m2_dat_o=>timer_wb.wdata,
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m2_dat_i=>timer_wb.rdata,
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m2_dat_i=>timer_wb.rdata,
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|
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m3_cyc_o=>coprocessor_wb.cyc,
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m3_cyc_o=>coprocessor_wb.cyc,
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m3_stb_o=>coprocessor_wb.stb,
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m3_stb_o=>coprocessor_wb.stb,
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m3_we_o=>coprocessor_wb.we,
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m3_we_o=>coprocessor_wb.we,
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m3_sel_o=>coprocessor_wb.sel,
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m3_sel_o=>coprocessor_wb.sel,
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m3_ack_i=>coprocessor_wb.ack,
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m3_ack_i=>coprocessor_wb.ack,
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m3_adr_o=>coprocessor_wb.adr,
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m3_adr_o=>coprocessor_wb.adr,
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m3_dat_o=>coprocessor_wb.wdata,
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m3_dat_o=>coprocessor_wb.wdata,
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m3_dat_i=>coprocessor_wb.rdata
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m3_dat_i=>coprocessor_wb.rdata
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);
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);
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|
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-- CPU
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-- CPU
|
|
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cpu_rst<=cpu_rst_i or rst_i;
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cpu_rst<=cpu_rst_i or rst_i;
|
|
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-- Note: we connect the timer IRQ to 2 CPU channels to test
|
-- Note: we connect the timer IRQ to 2 CPU channels to test
|
-- handling of simultaneously arriving interrupt requests.
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-- handling of simultaneously arriving interrupt requests.
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|
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cpu_irq<="00000"&coprocessor_irq&timer_elapsed&timer_elapsed;
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cpu_irq<="00000"&coprocessor_irq&timer_elapsed&timer_elapsed;
|
|
|
gen_lxp32u: if not MODEL_LXP32C generate
|
gen_lxp32u: if not MODEL_LXP32C generate
|
lxp32u_top_inst: entity work.lxp32u_top(rtl)
|
lxp32u_top_inst: entity work.lxp32u_top(rtl)
|
generic map(
|
generic map(
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DBUS_RMW=>CPU_DBUS_RMW,
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DBUS_RMW=>CPU_DBUS_RMW,
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DIVIDER_EN=>true,
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DIVIDER_EN=>true,
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MUL_ARCH=>CPU_MUL_ARCH,
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MUL_ARCH=>CPU_MUL_ARCH,
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START_ADDR=>(others=>'0')
|
START_ADDR=>(others=>'0')
|
)
|
)
|
port map(
|
port map(
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clk_i=>clk_i,
|
clk_i=>clk_i,
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rst_i=>cpu_rst,
|
rst_i=>cpu_rst,
|
|
|
lli_re_o=>lli_re,
|
lli_re_o=>lli_re,
|
lli_adr_o=>lli_adr,
|
lli_adr_o=>lli_adr,
|
lli_dat_i=>lli_dat,
|
lli_dat_i=>lli_dat,
|
lli_busy_i=>lli_busy,
|
lli_busy_i=>lli_busy,
|
|
|
dbus_cyc_o=>cpu_dbus.cyc,
|
dbus_cyc_o=>cpu_dbus.cyc,
|
dbus_stb_o=>cpu_dbus.stb,
|
dbus_stb_o=>cpu_dbus.stb,
|
dbus_we_o=>cpu_dbus.we,
|
dbus_we_o=>cpu_dbus.we,
|
dbus_sel_o=>cpu_dbus.sel,
|
dbus_sel_o=>cpu_dbus.sel,
|
dbus_ack_i=>cpu_dbus.ack,
|
dbus_ack_i=>cpu_dbus.ack,
|
dbus_adr_o=>cpu_dbus.adr,
|
dbus_adr_o=>cpu_dbus.adr,
|
dbus_dat_o=>cpu_dbus.wdata,
|
dbus_dat_o=>cpu_dbus.wdata,
|
dbus_dat_i=>cpu_dbus.rdata,
|
dbus_dat_i=>cpu_dbus.rdata,
|
|
|
irq_i=>cpu_irq
|
irq_i=>cpu_irq
|
);
|
);
|
end generate;
|
end generate;
|
|
|
gen_lxp32c: if MODEL_LXP32C generate
|
gen_lxp32c: if MODEL_LXP32C generate
|
lxp32c_top_inst: entity work.lxp32c_top(rtl)
|
lxp32c_top_inst: entity work.lxp32c_top(rtl)
|
generic map(
|
generic map(
|
DBUS_RMW=>CPU_DBUS_RMW,
|
DBUS_RMW=>CPU_DBUS_RMW,
|
DIVIDER_EN=>true,
|
DIVIDER_EN=>true,
|
IBUS_BURST_SIZE=>16,
|
IBUS_BURST_SIZE=>16,
|
IBUS_PREFETCH_SIZE=>32,
|
IBUS_PREFETCH_SIZE=>32,
|
MUL_ARCH=>CPU_MUL_ARCH,
|
MUL_ARCH=>CPU_MUL_ARCH,
|
START_ADDR=>(others=>'0')
|
START_ADDR=>(others=>'0')
|
)
|
)
|
port map(
|
port map(
|
clk_i=>clk_i,
|
clk_i=>clk_i,
|
rst_i=>cpu_rst,
|
rst_i=>cpu_rst,
|
|
|
ibus_cyc_o=>cpu_ibus.cyc,
|
ibus_cyc_o=>cpu_ibus.cyc,
|
ibus_stb_o=>cpu_ibus.stb,
|
ibus_stb_o=>cpu_ibus.stb,
|
ibus_cti_o=>cpu_ibus.cti,
|
ibus_cti_o=>cpu_ibus.cti,
|
ibus_bte_o=>cpu_ibus.bte,
|
ibus_bte_o=>cpu_ibus.bte,
|
ibus_ack_i=>cpu_ibus.ack,
|
ibus_ack_i=>cpu_ibus.ack,
|
ibus_adr_o=>cpu_ibus.adr,
|
ibus_adr_o=>cpu_ibus.adr,
|
ibus_dat_i=>cpu_ibus.dat,
|
ibus_dat_i=>cpu_ibus.dat,
|
|
|
dbus_cyc_o=>cpu_dbus.cyc,
|
dbus_cyc_o=>cpu_dbus.cyc,
|
dbus_stb_o=>cpu_dbus.stb,
|
dbus_stb_o=>cpu_dbus.stb,
|
dbus_we_o=>cpu_dbus.we,
|
dbus_we_o=>cpu_dbus.we,
|
dbus_sel_o=>cpu_dbus.sel,
|
dbus_sel_o=>cpu_dbus.sel,
|
dbus_ack_i=>cpu_dbus.ack,
|
dbus_ack_i=>cpu_dbus.ack,
|
dbus_adr_o=>cpu_dbus.adr,
|
dbus_adr_o=>cpu_dbus.adr,
|
dbus_dat_o=>cpu_dbus.wdata,
|
dbus_dat_o=>cpu_dbus.wdata,
|
dbus_dat_i=>cpu_dbus.rdata,
|
dbus_dat_i=>cpu_dbus.rdata,
|
|
|
irq_i=>cpu_irq
|
irq_i=>cpu_irq
|
);
|
);
|
|
|
ibus_adapter_inst: entity work.ibus_adapter(rtl)
|
ibus_adapter_inst: entity work.ibus_adapter(rtl)
|
port map(
|
port map(
|
clk_i=>clk_i,
|
clk_i=>clk_i,
|
rst_i=>rst_i,
|
rst_i=>rst_i,
|
|
|
ibus_cyc_i=>cpu_ibus.cyc,
|
ibus_cyc_i=>cpu_ibus.cyc,
|
ibus_stb_i=>cpu_ibus.stb,
|
ibus_stb_i=>cpu_ibus.stb,
|
ibus_cti_i=>cpu_ibus.cti,
|
ibus_cti_i=>cpu_ibus.cti,
|
ibus_bte_i=>cpu_ibus.bte,
|
ibus_bte_i=>cpu_ibus.bte,
|
ibus_ack_o=>cpu_ibus.ack,
|
ibus_ack_o=>cpu_ibus.ack,
|
ibus_adr_i=>cpu_ibus.adr,
|
ibus_adr_i=>cpu_ibus.adr,
|
ibus_dat_o=>cpu_ibus.dat,
|
ibus_dat_o=>cpu_ibus.dat,
|
|
|
lli_re_o=>lli_re,
|
lli_re_o=>lli_re,
|
lli_adr_o=>lli_adr,
|
lli_adr_o=>lli_adr,
|
lli_dat_i=>lli_dat,
|
lli_dat_i=>lli_dat,
|
lli_busy_i=>lli_busy
|
lli_busy_i=>lli_busy
|
);
|
);
|
end generate;
|
end generate;
|
|
|
-- DBUS monitor
|
-- DBUS monitor
|
|
|
dbus_monitor_inst: entity work.dbus_monitor(rtl)
|
dbus_monitor_inst: entity work.dbus_monitor(rtl)
|
generic map(
|
generic map(
|
THROTTLE=>THROTTLE_DBUS
|
THROTTLE=>THROTTLE_DBUS
|
)
|
)
|
port map(
|
port map(
|
clk_i=>clk_i,
|
clk_i=>clk_i,
|
rst_i=>rst_i,
|
rst_i=>rst_i,
|
|
|
wbs_cyc_i=>cpu_dbus.cyc,
|
wbs_cyc_i=>cpu_dbus.cyc,
|
wbs_stb_i=>cpu_dbus.stb,
|
wbs_stb_i=>cpu_dbus.stb,
|
wbs_we_i=>cpu_dbus.we,
|
wbs_we_i=>cpu_dbus.we,
|
wbs_sel_i=>cpu_dbus.sel,
|
wbs_sel_i=>cpu_dbus.sel,
|
wbs_ack_o=>cpu_dbus.ack,
|
wbs_ack_o=>cpu_dbus.ack,
|
wbs_adr_i=>cpu_dbus.adr,
|
wbs_adr_i=>cpu_dbus.adr,
|
wbs_dat_i=>cpu_dbus.wdata,
|
wbs_dat_i=>cpu_dbus.wdata,
|
wbs_dat_o=>cpu_dbus.rdata,
|
wbs_dat_o=>cpu_dbus.rdata,
|
|
|
wbm_cyc_o=>monitor_dbus.cyc,
|
wbm_cyc_o=>monitor_dbus.cyc,
|
wbm_stb_o=>monitor_dbus.stb,
|
wbm_stb_o=>monitor_dbus.stb,
|
wbm_we_o=>monitor_dbus.we,
|
wbm_we_o=>monitor_dbus.we,
|
wbm_sel_o=>monitor_dbus.sel,
|
wbm_sel_o=>monitor_dbus.sel,
|
wbm_ack_i=>monitor_dbus.ack,
|
wbm_ack_i=>monitor_dbus.ack,
|
wbm_adr_o=>monitor_dbus.adr,
|
wbm_adr_o=>monitor_dbus.adr,
|
wbm_dat_o=>monitor_dbus.wdata,
|
wbm_dat_o=>monitor_dbus.wdata,
|
wbm_dat_i=>monitor_dbus.rdata
|
wbm_dat_i=>monitor_dbus.rdata
|
);
|
);
|
|
|
-- Program RAM
|
-- Program RAM
|
|
|
program_ram_inst: entity work.program_ram(rtl)
|
program_ram_inst: entity work.program_ram(rtl)
|
generic map(
|
generic map(
|
THROTTLE=>THROTTLE_IBUS
|
THROTTLE=>THROTTLE_IBUS
|
)
|
)
|
port map(
|
port map(
|
clk_i=>clk_i,
|
clk_i=>clk_i,
|
rst_i=>rst_i,
|
rst_i=>rst_i,
|
|
|
wbs_cyc_i=>ram_wb.cyc,
|
wbs_cyc_i=>ram_wb.cyc,
|
wbs_stb_i=>ram_wb.stb,
|
wbs_stb_i=>ram_wb.stb,
|
wbs_we_i=>ram_wb.we,
|
wbs_we_i=>ram_wb.we,
|
wbs_sel_i=>ram_wb.sel,
|
wbs_sel_i=>ram_wb.sel,
|
wbs_ack_o=>ram_wb.ack,
|
wbs_ack_o=>ram_wb.ack,
|
wbs_adr_i=>ram_wb.adr,
|
wbs_adr_i=>ram_wb.adr,
|
wbs_dat_i=>ram_wb.wdata,
|
wbs_dat_i=>ram_wb.wdata,
|
wbs_dat_o=>ram_wb.rdata,
|
wbs_dat_o=>ram_wb.rdata,
|
|
|
lli_re_i=>lli_re,
|
lli_re_i=>lli_re,
|
lli_adr_i=>lli_adr,
|
lli_adr_i=>lli_adr,
|
lli_dat_o=>lli_dat,
|
lli_dat_o=>lli_dat,
|
lli_busy_o=>lli_busy
|
lli_busy_o=>lli_busy
|
);
|
);
|
|
|
-- Timer
|
-- Timer
|
|
|
timer_inst: entity work.timer(rtl)
|
timer_inst: entity work.timer(rtl)
|
port map(
|
port map(
|
clk_i=>clk_i,
|
clk_i=>clk_i,
|
rst_i=>rst_i,
|
rst_i=>rst_i,
|
|
|
wbs_cyc_i=>timer_wb.cyc,
|
wbs_cyc_i=>timer_wb.cyc,
|
wbs_stb_i=>timer_wb.stb,
|
wbs_stb_i=>timer_wb.stb,
|
wbs_we_i=>timer_wb.we,
|
wbs_we_i=>timer_wb.we,
|
wbs_sel_i=>timer_wb.sel,
|
wbs_sel_i=>timer_wb.sel,
|
wbs_ack_o=>timer_wb.ack,
|
wbs_ack_o=>timer_wb.ack,
|
wbs_adr_i=>timer_wb.adr,
|
wbs_adr_i=>timer_wb.adr,
|
wbs_dat_i=>timer_wb.wdata,
|
wbs_dat_i=>timer_wb.wdata,
|
wbs_dat_o=>timer_wb.rdata,
|
wbs_dat_o=>timer_wb.rdata,
|
|
|
elapsed_o=>timer_elapsed
|
elapsed_o=>timer_elapsed
|
);
|
);
|
|
|
-- Coprocessor
|
-- Coprocessor
|
|
|
coprocessor_inst: entity work.coprocessor(rtl)
|
coprocessor_inst: entity work.coprocessor(rtl)
|
port map(
|
port map(
|
clk_i=>clk_i,
|
clk_i=>clk_i,
|
rst_i=>rst_i,
|
rst_i=>rst_i,
|
|
|
wbs_cyc_i=>coprocessor_wb.cyc,
|
wbs_cyc_i=>coprocessor_wb.cyc,
|
wbs_stb_i=>coprocessor_wb.stb,
|
wbs_stb_i=>coprocessor_wb.stb,
|
wbs_we_i=>coprocessor_wb.we,
|
wbs_we_i=>coprocessor_wb.we,
|
wbs_sel_i=>coprocessor_wb.sel,
|
wbs_sel_i=>coprocessor_wb.sel,
|
wbs_ack_o=>coprocessor_wb.ack,
|
wbs_ack_o=>coprocessor_wb.ack,
|
wbs_adr_i=>coprocessor_wb.adr,
|
wbs_adr_i=>coprocessor_wb.adr,
|
wbs_dat_i=>coprocessor_wb.wdata,
|
wbs_dat_i=>coprocessor_wb.wdata,
|
wbs_dat_o=>coprocessor_wb.rdata,
|
wbs_dat_o=>coprocessor_wb.rdata,
|
|
|
irq_o=>coprocessor_irq
|
irq_o=>coprocessor_irq
|
);
|
);
|
|
|
end architecture;
|
end architecture;
|
|
|
