---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- Program RAM
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-- Program RAM
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--
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--
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-- Part of the LXP32 test platform
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-- Part of the LXP32 test platform
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--
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--
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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--
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--
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-- Program RAM for the LXP32 test platform. Has two interfaces:
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-- Program RAM for the LXP32 test platform. Has two interfaces:
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-- WISHBONE (for data access) and LLI (for LXP32 instruction bus).
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-- WISHBONE (for data access) and LLI (for LXP32 instruction bus).
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-- Optionally performs throttling.
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-- Optionally performs throttling.
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--
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--
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-- Note: regardless of whether this description is synthesizable,
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-- Note: regardless of whether this description is synthesizable,
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-- it was designed exclusively for simulation purposes.
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-- it was designed exclusively for simulation purposes.
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use work.common_pkg.all;
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use work.common_pkg.all;
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entity program_ram is
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entity program_ram is
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generic(
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generic(
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THROTTLE: boolean
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THROTTLE: boolean
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);
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);
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port(
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port(
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clk_i: in std_logic;
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clk_i: in std_logic;
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rst_i: in std_logic;
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rst_i: in std_logic;
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wbs_cyc_i: in std_logic;
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wbs_cyc_i: in std_logic;
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wbs_stb_i: in std_logic;
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wbs_stb_i: in std_logic;
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wbs_we_i: in std_logic;
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wbs_we_i: in std_logic;
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wbs_sel_i: in std_logic_vector(3 downto 0);
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wbs_sel_i: in std_logic_vector(3 downto 0);
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wbs_ack_o: out std_logic;
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wbs_ack_o: out std_logic;
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wbs_adr_i: in std_logic_vector(27 downto 2);
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wbs_adr_i: in std_logic_vector(27 downto 2);
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wbs_dat_i: in std_logic_vector(31 downto 0);
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wbs_dat_i: in std_logic_vector(31 downto 0);
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wbs_dat_o: out std_logic_vector(31 downto 0);
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wbs_dat_o: out std_logic_vector(31 downto 0);
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lli_re_i: in std_logic;
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lli_re_i: in std_logic;
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lli_adr_i: in std_logic_vector(29 downto 0);
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lli_adr_i: in std_logic_vector(29 downto 0);
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lli_dat_o: out std_logic_vector(31 downto 0);
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lli_dat_o: out std_logic_vector(31 downto 0);
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lli_busy_o: out std_logic
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lli_busy_o: out std_logic
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);
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);
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end entity;
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end entity;
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architecture rtl of program_ram is
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architecture rtl of program_ram is
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signal ram_a_we: std_logic_vector(3 downto 0);
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signal ram_a_we: std_logic_vector(3 downto 0);
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signal ram_a_rdata: std_logic_vector(31 downto 0);
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signal ram_a_rdata: std_logic_vector(31 downto 0);
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signal ram_b_re: std_logic;
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signal ram_b_re: std_logic;
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signal ram_b_rdata: std_logic_vector(31 downto 0);
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signal ram_b_rdata: std_logic_vector(31 downto 0);
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signal ack_write: std_logic;
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signal ack_write: std_logic;
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signal ack_read: std_logic;
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signal ack_read: std_logic;
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signal prbs: std_logic;
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signal prbs: std_logic;
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signal lli_busy: std_logic:='0';
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signal lli_busy: std_logic:='0';
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begin
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begin
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-- The total memory size is 16384 words, i.e. 64K bytes
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-- The total memory size is 16384 words, i.e. 64K bytes
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gen_dprams: for i in 3 downto 0 generate
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gen_dprams: for i in 3 downto 0 generate
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generic_dpram_inst: entity work.generic_dpram(rtl)
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generic_dpram_inst: entity work.generic_dpram(rtl)
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generic map(
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generic map(
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DATA_WIDTH=>8,
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DATA_WIDTH=>8,
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ADDR_WIDTH=>14,
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ADDR_WIDTH=>14,
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SIZE=>16384,
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SIZE=>16384,
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MODE=>"DONTCARE"
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MODE=>"DONTCARE"
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)
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)
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port map(
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port map(
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clka_i=>clk_i,
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clka_i=>clk_i,
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cea_i=>'1',
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cea_i=>'1',
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wea_i=>ram_a_we(i),
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wea_i=>ram_a_we(i),
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addra_i=>wbs_adr_i(15 downto 2),
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addra_i=>wbs_adr_i(15 downto 2),
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da_i=>wbs_dat_i(i*8+7 downto i*8),
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da_i=>wbs_dat_i(i*8+7 downto i*8),
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da_o=>ram_a_rdata(i*8+7 downto i*8),
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da_o=>ram_a_rdata(i*8+7 downto i*8),
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clkb_i=>clk_i,
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clkb_i=>clk_i,
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ceb_i=>ram_b_re,
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ceb_i=>ram_b_re,
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addrb_i=>lli_adr_i(13 downto 0),
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addrb_i=>lli_adr_i(13 downto 0),
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db_o=>ram_b_rdata(i*8+7 downto i*8)
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db_o=>ram_b_rdata(i*8+7 downto i*8)
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);
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);
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end generate;
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end generate;
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-- WISHBONE interface
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-- WISHBONE interface
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gen_ram_a_we: for i in 3 downto 0 generate
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gen_ram_a_we: for i in 3 downto 0 generate
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ram_a_we(i)<='1' when wbs_cyc_i='1' and wbs_stb_i='1' and wbs_we_i='1'
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ram_a_we(i)<='1' when wbs_cyc_i='1' and wbs_stb_i='1' and wbs_we_i='1'
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and wbs_sel_i(i)='1' and wbs_adr_i(27 downto 16)="000000000000" else '0';
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and wbs_sel_i(i)='1' and wbs_adr_i(27 downto 16)="000000000000" else '0';
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end generate;
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end generate;
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process (clk_i) is
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process (clk_i) is
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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ack_read<=wbs_cyc_i and wbs_stb_i and not wbs_we_i and not ack_read;
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ack_read<=wbs_cyc_i and wbs_stb_i and not wbs_we_i and not ack_read;
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end if;
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end if;
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end process;
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end process;
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ack_write<=wbs_cyc_i and wbs_stb_i and wbs_we_i;
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ack_write<=wbs_cyc_i and wbs_stb_i and wbs_we_i;
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wbs_ack_o<=ack_read or ack_write;
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wbs_ack_o<=ack_read or ack_write;
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wbs_dat_o<=ram_a_rdata;
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wbs_dat_o<=ram_a_rdata;
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-- Low Latency Interface (with optional pseudo-random throttling)
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-- Low Latency Interface (with optional pseudo-random throttling)
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process (clk_i) is
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process (clk_i) is
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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assert lli_re_i='0' or lli_adr_i(lli_adr_i'high downto 14)=X"0000"
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assert lli_re_i='0' or lli_adr_i(lli_adr_i'high downto 14)=X"0000"
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report "Attempted to fetch instruction from a non-existent address 0x"&
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report "Attempted to fetch instruction from a non-existent address 0x"&
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hex_string(lli_adr_i&"00")
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hex_string(lli_adr_i&"00")
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severity failure;
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severity failure;
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end if;
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end if;
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end process;
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end process;
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gen_throttling: if THROTTLE generate
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gen_throttling: if THROTTLE generate
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throttle_inst: entity work.scrambler(rtl)
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throttle_inst: entity work.scrambler(rtl)
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generic map(TAP1=>9,TAP2=>11)
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generic map(TAP1=>9,TAP2=>11)
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port map(clk_i=>clk_i,rst_i=>rst_i,ce_i=>'1',d_o=>prbs);
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port map(clk_i=>clk_i,rst_i=>rst_i,ce_i=>'1',d_o=>prbs);
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end generate;
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end generate;
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gen_no_throttling: if not THROTTLE generate
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gen_no_throttling: if not THROTTLE generate
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prbs<='0';
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prbs<='0';
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end generate;
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end generate;
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process (clk_i) is
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process (clk_i) is
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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if rst_i='1' then
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if rst_i='1' then
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lli_busy<='0';
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lli_busy<='0';
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elsif prbs='1' and lli_re_i='1' then
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elsif prbs='1' and lli_re_i='1' then
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lli_busy<='1';
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lli_busy<='1';
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elsif prbs='0' then
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elsif prbs='0' then
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lli_busy<='0';
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lli_busy<='0';
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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ram_b_re<=lli_re_i and not lli_busy;
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ram_b_re<=lli_re_i and not lli_busy;
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lli_busy_o<=lli_busy;
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lli_busy_o<=lli_busy;
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lli_dat_o<=ram_b_rdata when lli_busy='0' else (others=>'-');
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lli_dat_o<=ram_b_rdata when lli_busy='0' else (others=>'-');
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end architecture;
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end architecture;
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