---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- LXP32 testbench package
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-- LXP32 testbench package
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--
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--
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-- Part of the LXP32 testbench
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-- Part of the LXP32 testbench
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--
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--
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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--
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--
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-- Auxiliary package declaration for the LXP32 testbench
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-- Auxiliary package declaration for the LXP32 testbench
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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package tb_pkg is
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package tb_pkg is
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constant c_max_program_size: integer:=8192;
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constant c_max_program_size: integer:=8192;
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type soc_globals_type is record
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type soc_globals_type is record
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rst_i: std_logic;
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rst_i: std_logic;
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cpu_rst_i: std_logic;
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cpu_rst_i: std_logic;
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end record;
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end record;
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type soc_wbs_in_type is record
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type soc_wbs_in_type is record
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cyc: std_logic;
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cyc: std_logic;
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stb: std_logic;
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stb: std_logic;
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we: std_logic;
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we: std_logic;
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sel: std_logic_vector(3 downto 0);
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sel: std_logic_vector(3 downto 0);
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adr: std_logic_vector(31 downto 2);
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adr: std_logic_vector(31 downto 2);
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dat: std_logic_vector(31 downto 0);
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dat: std_logic_vector(31 downto 0);
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end record;
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end record;
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type soc_wbs_out_type is record
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type soc_wbs_out_type is record
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ack: std_logic;
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ack: std_logic;
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dat: std_logic_vector(31 downto 0);
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dat: std_logic_vector(31 downto 0);
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end record;
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end record;
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type soc_wbm_in_type is record
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type soc_wbm_in_type is record
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ack: std_logic;
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ack: std_logic;
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dat: std_logic_vector(31 downto 0);
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dat: std_logic_vector(31 downto 0);
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end record;
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end record;
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type soc_wbm_out_type is record
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type soc_wbm_out_type is record
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cyc: std_logic;
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cyc: std_logic;
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stb: std_logic;
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stb: std_logic;
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we: std_logic;
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we: std_logic;
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sel: std_logic_vector(3 downto 0);
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sel: std_logic_vector(3 downto 0);
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adr: std_logic_vector(27 downto 2);
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adr: std_logic_vector(27 downto 2);
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dat: std_logic_vector(31 downto 0);
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dat: std_logic_vector(31 downto 0);
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end record;
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end record;
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type monitor_out_type is record
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type monitor_out_type is record
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data: std_logic_vector(31 downto 0);
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data: std_logic_vector(31 downto 0);
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valid: std_logic;
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valid: std_logic;
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end record;
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end record;
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procedure load_ram(
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procedure load_ram(
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filename: string;
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filename: string;
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signal clk: in std_logic;
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signal clk: in std_logic;
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signal soc_in: out soc_wbs_in_type;
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signal soc_in: out soc_wbs_in_type;
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signal soc_out: in soc_wbs_out_type
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signal soc_out: in soc_wbs_out_type
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);
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);
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procedure run_test(
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procedure run_test(
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filename: string;
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filename: string;
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signal clk: in std_logic;
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signal clk: in std_logic;
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signal globals: out soc_globals_type;
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signal globals: out soc_globals_type;
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signal soc_in: out soc_wbs_in_type;
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signal soc_in: out soc_wbs_in_type;
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signal soc_out: in soc_wbs_out_type;
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signal soc_out: in soc_wbs_out_type;
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signal result: in monitor_out_type
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signal result: in monitor_out_type
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);
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);
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end package;
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end package;
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