MPASM 5.50 M16C5X_TST4.ASM 7-28-2013 12:14:21 PAGE 1
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MPASM 5.50 M16C5X_TST4.ASM 12-5-2013 8:25:30 PAGE 1
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LOC OBJECT CODE LINE SOURCE TEXT
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LOC OBJECT CODE LINE SOURCE TEXT
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VALUE
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VALUE
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00001 ;*******************************************************************************
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00001 ;*******************************************************************************
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00002 ; M16C5x_Tst4.ASM
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00002 ; M16C5x_Tst4.ASM
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00003 ;
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00003 ;
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00004 ;
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00004 ;
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00005 ; This program tests the receive function of the SSP UART.
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00005 ; This program tests the receive function of the SSP UART.
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00006 ;
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00006 ;
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00007 ; The UART is polled to determine if there is a Rx character available. If a
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00007 ; The UART is polled to determine if there is a Rx character available. If a
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00008 ; Rx character is available, the character is read from the UART RHR (Rx FIFO)
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00008 ; Rx character is available, the character is read from the UART RHR (Rx FIFO)
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00009 ; into a temporary location in the register file. The received character is
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00009 ; into a temporary location in the register file. The received character is
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00010 ; checked for upper/lower case. If it is an upper case character, the charac-
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00010 ; checked for upper/lower case. If it is an upper case character, the charac-
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00011 ; ter is converted to lower case. If it is a lower case character, the charac-
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00011 ; ter is converted to lower case. If it is a lower case character, the charac-
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00012 ; ter is converter to upper case. After conversion, the character is sent to
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00012 ; ter is converter to upper case. After conversion, the character is sent to
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00013 ; the UART's Tx FIFO.
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00013 ; the UART's Tx FIFO.
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00014 ;
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00014 ;
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00015 ;*******************************************************************************
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00015 ;*******************************************************************************
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00016
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00016
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00017 LIST P=16F59, R=DEC
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00017 LIST P=16F59, R=DEC
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00018
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00018
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00019 ;-------------------------------------------------------------------------------
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00019 ;-------------------------------------------------------------------------------
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00020 ; Set ScratchPadRam here. If you are using a PIC16C5X device, use:
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00020 ; Set ScratchPadRam here. If you are using a PIC16C5X device, use:
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00021 ;ScratchPadRam EQU 0x10
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00021 ;ScratchPadRam EQU 0x10
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00022 ; Otherwise, use:
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00022 ; Otherwise, use:
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00023 ;ScratchPadRam EQU 0x20
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00023 ;ScratchPadRam EQU 0x20
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00024 ;-------------------------------------------------------------------------------
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00024 ;-------------------------------------------------------------------------------
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00025
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00025
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00000010 00026 ScratchPadRAM EQU 0x10
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00000010 00026 ScratchPadRAM EQU 0x10
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00027
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00027
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00028 ;-------------------------------------------------------------------------------
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00028 ;-------------------------------------------------------------------------------
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00029 ; Variables
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00029 ; Variables
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00030 ;-------------------------------------------------------------------------------
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00030 ;-------------------------------------------------------------------------------
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00031
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00031
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00000000 00032 INDF EQU 0 ; Indirect Register File Access Location
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00000000 00032 INDF EQU 0 ; Indirect Register File Access Location
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00000001 00033 Tmr0 EQU 1 ; Timer 0
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00000001 00033 Tmr0 EQU 1 ; Timer 0
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00000002 00034 PCL EQU 2 ; Low Byte Program Counter
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00000002 00034 PCL EQU 2 ; Low Byte Program Counter
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00000003 00035 Status EQU 3 ; Processor Status Register
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00000003 00035 Status EQU 3 ; Processor Status Register
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00000004 00036 FSR EQU 4 ; File Select Register
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00000004 00036 FSR EQU 4 ; File Select Register
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00000005 00037 PortA EQU 5 ; I/O Port A Address
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00000005 00037 PortA EQU 5 ; I/O Port A Address
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00000006 00038 PortB EQU 6 ; I/O Port B Address
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00000006 00038 PortB EQU 6 ; I/O Port B Address
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00000007 00039 PortC EQU 7 ; I/O Port C Address
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00000007 00039 PortC EQU 7 ; I/O Port C Address
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00040
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00040
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0000000A 00041 SPI_CR EQU 0x0A ; SPI Control Register Shadow/Working Copy
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0000000A 00041 SPI_CR EQU 0x0A ; SPI Control Register Shadow/Working Copy
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0000000B 00042 SPI_SR EQU 0x0B ; SPI Status Register Shadow/Working Copy
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0000000B 00042 SPI_SR EQU 0x0B ; SPI Status Register Shadow/Working Copy
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0000000C 00043 SPI_DIO_H EQU 0x0C ; 1st byte To/From from SPI Rcv FIFO
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0000000C 00043 SPI_DIO_H EQU 0x0C ; 1st byte To/From from SPI Rcv FIFO
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0000000D 00044 SPI_DIO_L EQU 0x0D ; 2nd byte To/From from SPI Rcv FIFO
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0000000D 00044 SPI_DIO_L EQU 0x0D ; 2nd byte To/From from SPI Rcv FIFO
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00045
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00045
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0000000F 00046 DlyCntr EQU 0x0F ; General Purpose Delay Counter Register
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0000000F 00046 DlyCntr EQU 0x0F ; General Purpose Delay Counter Register
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00047
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00047
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00048 ;-------------------------------------------------------------------------------
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00048 ;-------------------------------------------------------------------------------
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00049 ; SPI Control Register Bit Map (M16C5x TRIS A register)
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00049 ; SPI Control Register Bit Map (M16C5x TRIS A register)
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00050 ;-------------------------------------------------------------------------------
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00050 ;-------------------------------------------------------------------------------
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00051
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00051
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00000000 00052 SPI_CR_REn EQU 0 ; Enable MISO Data Capture
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00000000 00052 SPI_CR_REn EQU 0 ; Enable MISO Data Capture
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00000001 00053 SPI_CR_SSel EQU 1 ; Slv Select: 0 - Ext SEEPROM, 1 - SSP_UART
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00000001 00053 SPI_CR_SSel EQU 1 ; Slv Select: 0 - Ext SEEPROM, 1 - SSP_UART
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MPASM 5.50 M16C5X_TST4.ASM 7-28-2013 12:14:21 PAGE 2
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MPASM 5.50 M16C5X_TST4.ASM 12-5-2013 8:25:30 PAGE 2
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LOC OBJECT CODE LINE SOURCE TEXT
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LOC OBJECT CODE LINE SOURCE TEXT
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VALUE
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VALUE
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00000002 00054 SPI_CR_MD0 EQU 2 ; SPI Md[1:0]: UART - Mode 0 or Mode 3
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00000002 00054 SPI_CR_MD0 EQU 2 ; SPI Md[1:0]: UART - Mode 0 or Mode 3
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00000003 00055 SPI_CR_MD1 EQU 3 ; SEEPROM - Mode 0 or Mode 3
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00000003 00055 SPI_CR_MD1 EQU 3 ; SEEPROM - Mode 0 or Mode 3
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00000004 00056 SPI_CR_BR0 EQU 4 ; SPI Baud Rate: 0 - Clk/2, ... Clk/128
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00000004 00056 SPI_CR_BR0 EQU 4 ; SPI Baud Rate: 0 - Clk/2, ... Clk/128
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00000005 00057 SPI_CR_BR1 EQU 5 ; Default: 110 - Clk/64
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00000005 00057 SPI_CR_BR1 EQU 5 ; Default: 110 - Clk/64
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00000006 00058 SPI_CR_BR2 EQU 6 ; Clk/2 29.4912 MHz
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00000006 00058 SPI_CR_BR2 EQU 6 ; Clk/2 29.4912 MHz
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00000007 00059 SPI_CR_DIR EQU 7 ; SPI Shift Direction: 0 - MSB, 1 - LSB
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00000007 00059 SPI_CR_DIR EQU 7 ; SPI Shift Direction: 0 - MSB, 1 - LSB
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00060
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00060
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00061 ;-------------------------------------------------------------------------------
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00061 ;-------------------------------------------------------------------------------
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00062 ; SPI Status Register Bit Map (M16C5x Port A input)
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00062 ; SPI Status Register Bit Map (M16C5x Port A input)
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00063 ;-------------------------------------------------------------------------------
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00063 ;-------------------------------------------------------------------------------
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00064
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00064
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00000000 00065 SPI_SR_TF_EF EQU 0 ; SPI TF Empty Flag (All Data Transmitted)
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00000000 00065 SPI_SR_TF_EF EQU 0 ; SPI TF Empty Flag (All Data Transmitted)
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00000001 00066 SPI_SR_TF_FF EQU 1 ; SPI TF Full Flag (Possible Overrun Error)
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00000001 00066 SPI_SR_TF_FF EQU 1 ; SPI TF Full Flag (Possible Overrun Error)
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00000002 00067 SPI_SR_RF_EF EQU 2 ; SPI RF Empty Flag (Data Available)
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00000002 00067 SPI_SR_RF_EF EQU 2 ; SPI RF Empty Flag (Data Available)
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00000003 00068 SPI_SR_RF_FF EQU 3 ; SPI RF Full Flag (Possible Overrun Error)
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00000003 00068 SPI_SR_RF_FF EQU 3 ; SPI RF Full Flag (Possible Overrun Error)
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00000004 00069 SPI_SR_DE EQU 4 ; SSP UART RS-485 Drive Enable
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00000004 00069 SPI_SR_DE EQU 4 ; SSP UART RS-485 Drive Enable
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00000005 00070 SPI_SR_RTS EQU 5 ; SSP UART Request-To-Send Modem Control Out
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00000005 00070 SPI_SR_RTS EQU 5 ; SSP UART Request-To-Send Modem Control Out
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00000006 00071 SPI_SR_CTS EQU 6 ; SSP UART Clear-To-Send Modem Control Input
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00000006 00071 SPI_SR_CTS EQU 6 ; SSP UART Clear-To-Send Modem Control Input
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00000007 00072 SPI_SR_IRQ EQU 7 ; SSP UART Interrupt Request Output
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00000007 00072 SPI_SR_IRQ EQU 7 ; SSP UART Interrupt Request Output
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00073
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00073
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00074 ;-------------------------------------------------------------------------------
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00074 ;-------------------------------------------------------------------------------
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00075 ; SSP UART Control Register (RA = 000) (16-bits Total) (Read-Write)
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00075 ; SSP UART Control Register (RA = 000) (16-bits Total) (Read-Write)
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00076 ;-------------------------------------------------------------------------------
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00076 ;-------------------------------------------------------------------------------
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00077
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00077
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00000003 00078 UART_CR_RA EQU 3 ; Bits 7:5 SPI_DIO_H
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00000003 00078 UART_CR_RA EQU 3 ; Bits 7:5 SPI_DIO_H
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00000001 00079 UART_CR_WnR EQU 1 ; Bit 4 SPI_DIO_H, if Set Wr, else Rd
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00000001 00079 UART_CR_WnR EQU 1 ; Bit 4 SPI_DIO_H, if Set Wr, else Rd
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00000002 00080 UART_CR_MD EQU 2 ; Bits 3:2 SPI_DIO_H, UART Mode: 232/485
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00000002 00080 UART_CR_MD EQU 2 ; Bits 3:2 SPI_DIO_H, UART Mode: 232/485
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00000001 00081 UART_CR_RTSo EQU 1 ; Bit 1 SPI_DIO_H, Request-To-Send Output
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00000001 00081 UART_CR_RTSo EQU 1 ; Bit 1 SPI_DIO_H, Request-To-Send Output
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00000001 00082 UART_CR_IE EQU 1 ; Bit 0 SPI_DIO_H, Interrupt Enable
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00000001 00082 UART_CR_IE EQU 1 ; Bit 0 SPI_DIO_H, Interrupt Enable
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00000004 00083 UART_CR_FMT EQU 4 ; Bits 7:4 SPI_DIO_L, Serial Frame Format
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00000004 00083 UART_CR_FMT EQU 4 ; Bits 7:4 SPI_DIO_L, Serial Frame Format
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00000004 00084 UART_CR_BAUD EQU 4 ; Bits 3:0 SPI_DIO_L, Serial Baud Rate
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00000004 00084 UART_CR_BAUD EQU 4 ; Bits 3:0 SPI_DIO_L, Serial Baud Rate
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00085
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00085
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00086 ;-------------------------------------------------------------------------------
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00086 ;-------------------------------------------------------------------------------
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00087 ; SSP UART Status Register (RA = 001) (16-bits Total) (Read-Only)
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00087 ; SSP UART Status Register (RA = 001) (16-bits Total) (Read-Only)
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00088 ;-------------------------------------------------------------------------------
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00088 ;-------------------------------------------------------------------------------
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00089
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00089
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00000003 00090 UART_SR_RA EQU 3 ; Bits 7:5 SPI_DIO_H
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00000003 00090 UART_SR_RA EQU 3 ; Bits 7:5 SPI_DIO_H
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00000001 00091 UART_SR_WnR EQU 1 ; Bit 4 SPI_DIO_H, Ignored if Set
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00000001 00091 UART_SR_WnR EQU 1 ; Bit 4 SPI_DIO_H, Ignored if Set
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00000002 00092 UART_SR_MD EQU 2 ; Bits 3:2 SPI_DIO_H, UART Mode
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00000002 00092 UART_SR_MD EQU 2 ; Bits 3:2 SPI_DIO_H, UART Mode
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00000001 00093 UART_SR_RTSi EQU 1 ; Bit 1 SPI_DIO_H, RTS signal level
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00000001 00093 UART_SR_RTSi EQU 1 ; Bit 1 SPI_DIO_H, RTS signal level
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00000001 00094 UART_SR_CTSi EQU 1 ; Bit 0 SPI_DIO_H, CTS signal level
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00000001 00094 UART_SR_CTSi EQU 1 ; Bit 0 SPI_DIO_H, CTS signal level
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00000002 00095 UART_SR_RS EQU 2 ; Bits 7:6 SPI_DIO_L, Rx FIFO State
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00000002 00095 UART_SR_RS EQU 2 ; Bits 7:6 SPI_DIO_L, Rx FIFO State
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00000002 00096 UART_SR_TS EQU 2 ; Bits 5:4 SPI_DIO_L, Tx FIFO State
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00000002 00096 UART_SR_TS EQU 2 ; Bits 5:4 SPI_DIO_L, Tx FIFO State
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00000001 00097 UART_SR_iRTO EQU 1 ; Bit 3 SPI_DIO_L, Rcv Timeout Interrupt
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00000001 00097 UART_SR_iRTO EQU 1 ; Bit 3 SPI_DIO_L, Rcv Timeout Interrupt
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00000001 00098 UART_SR_iRDA EQU 1 ; Bit 2 SPI_DIO_L, Rcv Data Available
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00000001 00098 UART_SR_iRDA EQU 1 ; Bit 2 SPI_DIO_L, Rcv Data Available
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00000001 00099 UART_SR_iTHE EQU 1 ; Bit 1 SPI_DIO_L, Tx FIFO Half Empty
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00000001 00099 UART_SR_iTHE EQU 1 ; Bit 1 SPI_DIO_L, Tx FIFO Half Empty
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00000001 00100 UART_SR_iTFE EQU 1 ; Bit 0 SPI_DIO_L, Tx FIFO Empty
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00000001 00100 UART_SR_iTFE EQU 1 ; Bit 0 SPI_DIO_L, Tx FIFO Empty
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00101
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00101
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00102 ;-------------------------------------------------------------------------------
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00102 ;-------------------------------------------------------------------------------
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00103 ; SSP UART Baud Rate Register (RA = 001) (16-bits Total) (Write-Only)
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00103 ; SSP UART Baud Rate Register (RA = 001) (16-bits Total) (Write-Only)
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00104 ;-------------------------------------------------------------------------------
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00104 ;-------------------------------------------------------------------------------
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00105
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00105
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00000004 00106 UART_BR_PS EQU 4 ; Bits 11:8 : Baud rate prescaler - (M - 1)
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00000004 00106 UART_BR_PS EQU 4 ; Bits 11:8 : Baud rate prescaler - (M - 1)
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MPASM 5.50 M16C5X_TST4.ASM 7-28-2013 12:14:21 PAGE 3
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MPASM 5.50 M16C5X_TST4.ASM 12-5-2013 8:25:30 PAGE 3
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LOC OBJECT CODE LINE SOURCE TEXT
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LOC OBJECT CODE LINE SOURCE TEXT
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VALUE
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VALUE
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00000008 00107 UART_BR_Div EQU 8 ; Bits 7:0 : Baud rate divider - (N - 1)
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00000008 00107 UART_BR_Div EQU 8 ; Bits 7:0 : Baud rate divider - (N - 1)
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00108
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00108
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00109 ;-------------------------------------------------------------------------------
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00109 ;-------------------------------------------------------------------------------
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00110 ; SSP UART Transmit Data Register (RA = 010) (16-bits Total) (Write-Only)
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00110 ; SSP UART Transmit Data Register (RA = 010) (16-bits Total) (Write-Only)
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00111 ;-------------------------------------------------------------------------------
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00111 ;-------------------------------------------------------------------------------
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00112
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00112
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00000003 00113 UART_TD_RA EQU 3 ; Bits 7:5 SPI_DIO_H
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00000003 00113 UART_TD_RA EQU 3 ; Bits 7:5 SPI_DIO_H
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00000001 00114 UART_TD_WnR EQU 1 ; Bit 4 SPI_DIO_H, Ignored if Not Set
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00000001 00114 UART_TD_WnR EQU 1 ; Bit 4 SPI_DIO_H, Ignored if Not Set
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00000001 00115 UART_TD_TFC EQU 1 ; Bit 3 SPI_DIO_H, Transmit FIFO Clr/Rst
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00000001 00115 UART_TD_TFC EQU 1 ; Bit 3 SPI_DIO_H, Transmit FIFO Clr/Rst
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00000001 00116 UART_TD_RFC EQU 1 ; Bit 2 SPI_DIO_H, Receive FIFO Clr/Rst
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00000001 00116 UART_TD_RFC EQU 1 ; Bit 2 SPI_DIO_H, Receive FIFO Clr/Rst
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00000001 00117 UART_TD_HLD EQU 1 ; Bit 1 SPI_DIO_H, Tx delayed if Set
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00000001 00117 UART_TD_HLD EQU 1 ; Bit 1 SPI_DIO_H, Tx delayed if Set
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00000001 00118 UART_TD_Rsvd EQU 1 ; Bit 0 SPI_DIO_H, Reserved
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00000001 00118 UART_TD_Rsvd EQU 1 ; Bit 0 SPI_DIO_H, Reserved
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00000008 00119 UART_TD_DO EQU 8 ; Bits 7:0 SPI_DIO_L, Tx Data: 7 or 8 bits
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00000008 00119 UART_TD_DO EQU 8 ; Bits 7:0 SPI_DIO_L, Tx Data: 7 or 8 bits
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00120
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00120
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00121 ;-------------------------------------------------------------------------------
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00121 ;-------------------------------------------------------------------------------
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00122 ; SSP UART Recieve Data Register (RA = 011) (16-bits Total) (Read-Only)
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00122 ; SSP UART Recieve Data Register (RA = 011) (16-bits Total) (Read-Only)
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00123 ;-------------------------------------------------------------------------------
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00123 ;-------------------------------------------------------------------------------
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00124
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00124
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00000003 00125 UART_RD_RA EQU 3 ; Bits 7:5 SPI_DIO_H
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00000003 00125 UART_RD_RA EQU 3 ; Bits 7:5 SPI_DIO_H
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00000001 00126 UART_RD_WnR EQU 1 ; Bit 4 SPI_DIO_H, Ignored if Set
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00000001 00126 UART_RD_WnR EQU 1 ; Bit 4 SPI_DIO_H, Ignored if Set
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00000001 00127 UART_RD_TRDY EQU 1 ; Bit 3 SPI_DIO_H, Transmit Ready
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00000001 00127 UART_RD_TRDY EQU 1 ; Bit 3 SPI_DIO_H, Transmit Ready
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00000001 00128 UART_RD_RRDY EQU 1 ; Bit 2 SPI_DIO_H, Receive Ready
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00000001 00128 UART_RD_RRDY EQU 1 ; Bit 2 SPI_DIO_H, Receive Ready
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00000001 00129 UART_RD_RTO EQU 1 ; Bit 1 SPI_DIO_H, Receive Time Out Det.
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00000001 00129 UART_RD_RTO EQU 1 ; Bit 1 SPI_DIO_H, Receive Time Out Det.
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00000001 00130 UART_RD_RERR EQU 1 ; Bit 0 SPI_DIO_H, Receive Error Detect
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00000001 00130 UART_RD_RERR EQU 1 ; Bit 0 SPI_DIO_H, Receive Error Detect
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00000008 00131 UART_RD_DI EQU 8 ; Bits 7:0 SPI_DIO_L, Rx Data: 7 or 8 bits
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00000008 00131 UART_RD_DI EQU 8 ; Bits 7:0 SPI_DIO_L, Rx Data: 7 or 8 bits
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00132
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00132
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00133 ;-------------------------------------------------------------------------------
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00133 ;-------------------------------------------------------------------------------
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00134 ; Set Reset/WDT Vector
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00134 ; Set Reset/WDT Vector
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00135 ;-------------------------------------------------------------------------------
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00135 ;-------------------------------------------------------------------------------
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00136
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00136
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07FF 00137 ORG 0x7FF
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07FF 00137 ORG 0x7FF
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00138
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00138
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Message[306]: Crossing page boundary -- ensure page bits are set.
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Message[306]: Crossing page boundary -- ensure page bits are set.
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07FF 0A00 00139 GOTO Start
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07FF 0A00 00139 GOTO Start
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00140
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00140
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00141 ;-------------------------------------------------------------------------------
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00141 ;-------------------------------------------------------------------------------
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00142 ; Main Program
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00142 ; Main Program
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00143 ;-------------------------------------------------------------------------------
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00143 ;-------------------------------------------------------------------------------
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00144
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00144
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0000 00145 ORG 0x000
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0000 00145 ORG 0x000
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00146
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00146
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00147 ;-------------------------------------------------------------------------------
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00147 ;-------------------------------------------------------------------------------
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00148
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00148
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0000 0CFF 00149 Start MOVLW 0xFF ; Initialize TRIS A and TRIS B to all 1s
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0000 0CFF 00149 Start MOVLW 0xFF ; Initialize TRIS A and TRIS B to all 1s
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0001 0005 00150 TRIS 5
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0001 0005 00150 TRIS 5
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0002 0006 00151 TRIS 6
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0002 0006 00151 TRIS 6
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00152
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00152
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0003 0C1E 00153 MOVLW 0x1E ; Load W with SPI CR Initial Value
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0003 0C1E 00153 MOVLW 0x1E ; Load W with SPI CR Initial Value
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0004 002A 00154 MOVWF SPI_CR ; Save copy of value
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0004 002A 00154 MOVWF SPI_CR ; Save copy of value
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0005 0007 00155 TRIS 7 ; Initialize SPI CR
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0005 0007 00155 TRIS 7 ; Initialize SPI CR
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00156
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00156
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0006 0C08 00157 MOVLW 0x08 ; Delay before using SPI I/F
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0006 0C08 00157 MOVLW 0x08 ; Delay before using SPI I/F
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0007 002F 00158 MOVWF DlyCntr
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0007 002F 00158 MOVWF DlyCntr
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MPASM 5.50 M16C5X_TST4.ASM 7-28-2013 12:14:21 PAGE 4
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MPASM 5.50 M16C5X_TST4.ASM 12-5-2013 8:25:30 PAGE 4
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LOC OBJECT CODE LINE SOURCE TEXT
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LOC OBJECT CODE LINE SOURCE TEXT
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VALUE
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VALUE
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0008 02EF 00159 SPI_Init_Dly DECFSZ DlyCntr,1
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0008 02EF 00159 SPI_Init_Dly DECFSZ DlyCntr,1
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0009 0A08 00160 GOTO SPI_Init_Dly
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0009 0A08 00160 GOTO SPI_Init_Dly
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00161
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00161
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000A 0C13 00162 MOVLW 0x13 ; UART CR (Hi): RS232 2-wire, RTS, IE
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000A 0C13 00162 MOVLW 0x13 ; UART CR (Hi): RS232 2-wire, RTS, IE
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000B 0027 00163 MOVWF PortC ; Output to SPI and to UART
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000B 0027 00163 MOVWF PortC ; Output to SPI and to UART
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000C 0C00 00164 MOVLW 0x00 ; UART CR (Lo) Set 8N1
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000C 0C00 00164 MOVLW 0x00 ; UART CR (Lo) Set 8N1
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000D 0027 00165 MOVWF PortC
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000D 0027 00165 MOVWF PortC
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00166
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00166
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000E 0C30 00167 MOVLW 0x30 ; UART BRR (Hi) PS[3:0]
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000E 0C30 00167 MOVLW 0x30 ; UART BRR (Hi) PS[3:0]
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000F 0027 00168 MOVWF PortC ; Output to SPI and to UART
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000F 0027 00168 MOVWF PortC ; Output to SPI and to UART
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0010 0C0F 00169 MOVLW 0x0F ; UART BRR (Lo) Div[7:0] (115.2k baud)
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0010 0C01 00169 MOVLW 0x01 ; UART BRR (Lo) Div[7:0] (921.6k baud)
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0011 0027 00170 MOVWF PortC
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0011 0027 00170 MOVWF PortC
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00171
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00171
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0012 0705 00172 WaitLp1 BTFSS PortA,SPI_SR_TF_EF ; Wait for UART UCR, BRR output
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0012 0705 00172 WaitLp1 BTFSS PortA,SPI_SR_TF_EF ; Wait for UART UCR, BRR output
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0013 0A12 00173 GOTO WaitLp1
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0013 0A12 00173 GOTO WaitLp1
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00174
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00174
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00175 ;-------------------------------------------------------------------------------
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00175 ;-------------------------------------------------------------------------------
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00176
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00176
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0014 050A 00177 Rd_UART_RF BSF SPI_CR,SPI_CR_REn ; Enable SPI IF Capture MISO data
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0014 050A 00177 Rd_UART_RF BSF SPI_CR,SPI_CR_REn ; Enable SPI IF Capture MISO data
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00178
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00178
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0015 020A 00179 MOVF SPI_CR,0 ; Load SPI CR Shadow
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0015 020A 00179 MOVF SPI_CR,0 ; Load SPI CR Shadow
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0016 0007 00180 TRIS 7 ; Enable SPI I/F Receive Function
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0016 0007 00180 TRIS 7 ; Enable SPI I/F Receive Function
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00181
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00181
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0017 0C60 00182 Poll_UART_RF MOVLW 0x60 ; UART RF (Hi) RA = 3, WnR = 0
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0017 0C60 00182 Poll_UART_RF MOVLW 0x60 ; UART RF (Hi) RA = 3, WnR = 0
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0018 0027 00183 MOVWF PortC ; Output to SPI and to UART
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0018 0027 00183 MOVWF PortC ; Output to SPI and to UART
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0019 0CFF 00184 MOVLW 0xFF ; UART RD (Lo) 0xFF = "Del" or 0x00 (Nul)
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0019 0CFF 00184 MOVLW 0xFF ; UART RD (Lo) 0xFF = "Del" or 0x00 (Nul)
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001A 0027 00185 MOVWF PortC ; Output to SPI and to UART
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001A 0027 00185 MOVWF PortC ; Output to SPI and to UART
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00186
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00186
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001B 0705 00187 WaitLp2 BTFSS PortA,SPI_SR_TF_EF ; Wait for SPI TF to be empty
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001B 0705 00187 WaitLp2 BTFSS PortA,SPI_SR_TF_EF ; Wait for SPI TF to be empty
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001C 0A1B 00188 GOTO WaitLp2
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001C 0A1B 00188 GOTO WaitLp2
|
00189
|
00189
|
001D 0207 00190 MOVF PortC,0 ; Read SPI Receive FIFO
|
001D 0207 00190 MOVF PortC,0 ; Read SPI Receive FIFO
|
001E 002C 00191 MOVWF SPI_DIO_H ; Store UART SR (hi byte)
|
001E 002C 00191 MOVWF SPI_DIO_H ; Store UART SR (hi byte)
|
00192
|
00192
|
001F 0645 00193 WaitLp3 BTFSC PortA,SPI_SR_RF_EF ; Wait for UART Return Data (Hi)
|
001F 0645 00193 WaitLp3 BTFSC PortA,SPI_SR_RF_EF ; Wait for UART Return Data (Hi)
|
0020 0A1F 00194 GOTO WaitLp3
|
0020 0A1F 00194 GOTO WaitLp3
|
00195
|
00195
|
0021 0207 00196 MOVF PortC,0 ; Read SPI Receive FIFO
|
0021 0207 00196 MOVF PortC,0 ; Read SPI Receive FIFO
|
0022 002D 00197 MOVWF SPI_DIO_L ; Store UART SR (hi byte)
|
0022 002D 00197 MOVWF SPI_DIO_L ; Store UART SR (hi byte)
|
00198
|
00198
|
00199 ;-------------------------------------------------------------------------------
|
00199 ;-------------------------------------------------------------------------------
|
00200
|
00200
|
0023 074C 00201 Test_RD BTFSS SPI_DIO_H,2 ; Test RRDY bit, if Set, process RD
|
0023 074C 00201 Test_RD BTFSS SPI_DIO_H,2 ; Test RRDY bit, if Set, process RD
|
0024 0A17 00202 GOTO Poll_UART_RF ; Loop until character received
|
0024 0A17 00202 GOTO Poll_UART_RF ; Loop until character received
|
0025 060C 00203 BTFSC SPI_DIO_H,0 ; Test RD for error; if Set, discard
|
0025 060C 00203 BTFSC SPI_DIO_H,0 ; Test RD for error; if Set, discard
|
0026 0A17 00204 GOTO Poll_UART_RF ; Loop until error-free character rcvd
|
0026 0A17 00204 GOTO Poll_UART_RF ; Loop until error-free character rcvd
|
00205
|
00205
|
00206 ;-------------------------------------------------------------------------------
|
00206 ;-------------------------------------------------------------------------------
|
00207
|
00207
|
0027 06ED 00208 Tst_ExtASCII BTFSC SPI_DIO_L,7 ; Ignore Extended ASCII characters
|
0027 06ED 00208 Tst_ExtASCII BTFSC SPI_DIO_L,7 ; Ignore Extended ASCII characters
|
0028 0A3B 00209 GOTO Wr_UART_TF ; Transmit Extended ASCII as is
|
0028 0A3B 00209 GOTO Wr_UART_TF ; Transmit Extended ASCII as is
|
00210
|
00210
|
0029 0C7B 00211 Tst_LowerCase MOVLW 0x7B ; Test against 'z' + 1
|
0029 0C7B 00211 Tst_LowerCase MOVLW 0x7B ; Test against 'z' + 1
|
MPASM 5.50 M16C5X_TST4.ASM 7-28-2013 12:14:21 PAGE 5
|
MPASM 5.50 M16C5X_TST4.ASM 12-5-2013 8:25:30 PAGE 5
|
|
|
|
|
LOC OBJECT CODE LINE SOURCE TEXT
|
LOC OBJECT CODE LINE SOURCE TEXT
|
VALUE
|
VALUE
|
|
|
002A 008D 00212 SUBWF SPI_DIO_L,0 ; Compare RD against 'z'
|
002A 008D 00212 SUBWF SPI_DIO_L,0 ; Compare RD against 'z'
|
002B 0603 00213 BTFSC Status,0 ; If Status.C, RD > 'z'
|
002B 0603 00213 BTFSC Status,0 ; If Status.C, RD > 'z'
|
002C 0A3B 00214 GT_LowerCase GOTO Wr_UART_TF ; not upper or lower case, send data
|
002C 0A3B 00214 GT_LowerCase GOTO Wr_UART_TF ; not upper or lower case, send data
|
002D 0C61 00215 MOVLW 0x61 ; Load 'a'
|
002D 0C61 00215 MOVLW 0x61 ; Load 'a'
|
002E 008D 00216 SUBWF SPI_DIO_L,0 ; Compare RD against 'a'
|
002E 008D 00216 SUBWF SPI_DIO_L,0 ; Compare RD against 'a'
|
002F 0603 00217 BTFSC Status,0 ; Carry Set if RD >= 'a'
|
002F 0603 00217 BTFSC Status,0 ; Carry Set if RD >= 'a'
|
0030 0A39 00218 Is_LowerCase GOTO ChangeCase ; Is upper case, change case to lower
|
0030 0A39 00218 Is_LowerCase GOTO ChangeCase ; Is upper case, change case to lower
|
00219
|
00219
|
0031 0C5B 00220 Tst_UpperCase MOVLW 0x5B ; Test against 'Z' + 1
|
0031 0C5B 00220 Tst_UpperCase MOVLW 0x5B ; Test against 'Z' + 1
|
0032 008D 00221 SUBWF SPI_DIO_L,0 ; Compare RD against 'Z'
|
0032 008D 00221 SUBWF SPI_DIO_L,0 ; Compare RD against 'Z'
|
0033 0603 00222 BTFSC Status,0 ; Carry set if Rd > 'Z'
|
0033 0603 00222 BTFSC Status,0 ; Carry set if Rd > 'Z'
|
0034 0A3B 00223 Not_UpperLower GOTO Wr_UART_TF ; Not lower case
|
0034 0A3B 00223 Not_UpperLower GOTO Wr_UART_TF ; Not lower case
|
0035 0C41 00224 MOVLW 0x41 ; Load 'A'
|
0035 0C41 00224 MOVLW 0x41 ; Load 'A'
|
0036 008D 00225 SUBWF SPI_DIO_L,0 ; Compare against 'A'
|
0036 008D 00225 SUBWF SPI_DIO_L,0 ; Compare against 'A'
|
0037 0703 00226 BTFSS Status,0 ; Carry set if RD >= 'A'
|
0037 0703 00226 BTFSS Status,0 ; Carry set if RD >= 'A'
|
0038 0A3B 00227 LT_UpperCase GOTO Wr_UART_TF ; Tests complete, send data
|
0038 0A3B 00227 LT_UpperCase GOTO Wr_UART_TF ; Tests complete, send data
|
00228
|
00228
|
0039 00229 Is_UpperCase
|
0039 00229 Is_UpperCase
|
0039 0C20 00230 ChangeCase MOVLW 0x20 ; Change case: LC to UC, or UC to LC
|
0039 0C20 00230 ChangeCase MOVLW 0x20 ; Change case: LC to UC, or UC to LC
|
003A 01AD 00231 XORWF SPI_DIO_L,1
|
003A 01AD 00231 XORWF SPI_DIO_L,1
|
00232
|
00232
|
00233 ;-------------------------------------------------------------------------------
|
00233 ;-------------------------------------------------------------------------------
|
00234
|
00234
|
003B 040A 00235 Wr_UART_TF BCF SPI_CR,SPI_CR_REn ; Disable SPI IF Capture MISO data
|
003B 040A 00235 Wr_UART_TF BCF SPI_CR,SPI_CR_REn ; Disable SPI IF Capture MISO data
|
00236
|
00236
|
003C 020A 00237 MOVF SPI_CR,0 ; Load SPI CR Shadow
|
003C 020A 00237 MOVF SPI_CR,0 ; Load SPI CR Shadow
|
003D 0007 00238 TRIS 7 ; Enable SPI I/F Receive Function
|
003D 0007 00238 TRIS 7 ; Enable SPI I/F Receive Function
|
00239
|
00239
|
003E 0C50 00240 MOVLW 0x50 ; UART TF (Hi) RA = 2, WnR = 1
|
003E 0C50 00240 MOVLW 0x50 ; UART TF (Hi) RA = 2, WnR = 1
|
003F 0027 00241 MOVWF PortC ; Output to SPI and to UART
|
003F 0027 00241 MOVWF PortC ; Output to SPI and to UART
|
0040 020D 00242 MOVF SPI_DIO_L,0 ; Read data to transmit
|
0040 020D 00242 MOVF SPI_DIO_L,0 ; Read data to transmit
|
0041 0027 00243 MOVWF PortC ; Output to SPI TF and to UART
|
0041 0027 00243 MOVWF PortC ; Output to SPI TF and to UART
|
00244
|
00244
|
0042 0705 00245 WaitLp4 BTFSS PortA,SPI_SR_TF_EF ; Wait for SPI TF to be empty
|
0042 0705 00245 WaitLp4 BTFSS PortA,SPI_SR_TF_EF ; Wait for SPI TF to be empty
|
0043 0A42 00246 GOTO WaitLp4
|
0043 0A42 00246 GOTO WaitLp4
|
00247
|
00247
|
0044 0A14 00248 GOTO Rd_UART_RF ; Loop Forever, send 0x55 continously
|
0044 0A14 00248 GOTO Rd_UART_RF ; Loop Forever, send 0x55 continously
|
00249
|
00249
|
00250 ;-------------------------------------------------------------------------------
|
00250 ;-------------------------------------------------------------------------------
|
00251
|
00251
|
00252 END
|
00252 END
|
MPASM 5.50 M16C5X_TST4.ASM 7-28-2013 12:14:21 PAGE 6
|
MPASM 5.50 M16C5X_TST4.ASM 12-5-2013 8:25:30 PAGE 6
|
|
|
|
|
SYMBOL TABLE
|
SYMBOL TABLE
|
LABEL VALUE
|
LABEL VALUE
|
|
|
ChangeCase 00000039
|
ChangeCase 00000039
|
DlyCntr 0000000F
|
DlyCntr 0000000F
|
FSR 00000004
|
FSR 00000004
|
GT_LowerCase 0000002C
|
GT_LowerCase 0000002C
|
INDF 00000000
|
INDF 00000000
|
Is_LowerCase 00000030
|
Is_LowerCase 00000030
|
Is_UpperCase 00000039
|
Is_UpperCase 00000039
|
LT_UpperCase 00000038
|
LT_UpperCase 00000038
|
Not_UpperLower 00000034
|
Not_UpperLower 00000034
|
PCL 00000002
|
PCL 00000002
|
Poll_UART_RF 00000017
|
Poll_UART_RF 00000017
|
PortA 00000005
|
PortA 00000005
|
PortB 00000006
|
PortB 00000006
|
PortC 00000007
|
PortC 00000007
|
Rd_UART_RF 00000014
|
Rd_UART_RF 00000014
|
SPI_CR 0000000A
|
SPI_CR 0000000A
|
SPI_CR_BR0 00000004
|
SPI_CR_BR0 00000004
|
SPI_CR_BR1 00000005
|
SPI_CR_BR1 00000005
|
SPI_CR_BR2 00000006
|
SPI_CR_BR2 00000006
|
SPI_CR_DIR 00000007
|
SPI_CR_DIR 00000007
|
SPI_CR_MD0 00000002
|
SPI_CR_MD0 00000002
|
SPI_CR_MD1 00000003
|
SPI_CR_MD1 00000003
|
SPI_CR_REn 00000000
|
SPI_CR_REn 00000000
|
SPI_CR_SSel 00000001
|
SPI_CR_SSel 00000001
|
SPI_DIO_H 0000000C
|
SPI_DIO_H 0000000C
|
SPI_DIO_L 0000000D
|
SPI_DIO_L 0000000D
|
SPI_Init_Dly 00000008
|
SPI_Init_Dly 00000008
|
SPI_SR 0000000B
|
SPI_SR 0000000B
|
SPI_SR_CTS 00000006
|
SPI_SR_CTS 00000006
|
SPI_SR_DE 00000004
|
SPI_SR_DE 00000004
|
SPI_SR_IRQ 00000007
|
SPI_SR_IRQ 00000007
|
SPI_SR_RF_EF 00000002
|
SPI_SR_RF_EF 00000002
|
SPI_SR_RF_FF 00000003
|
SPI_SR_RF_FF 00000003
|
SPI_SR_RTS 00000005
|
SPI_SR_RTS 00000005
|
SPI_SR_TF_EF 00000000
|
SPI_SR_TF_EF 00000000
|
SPI_SR_TF_FF 00000001
|
SPI_SR_TF_FF 00000001
|
ScratchPadRAM 00000010
|
ScratchPadRAM 00000010
|
Start 00000000
|
Start 00000000
|
Status 00000003
|
Status 00000003
|
Test_RD 00000023
|
Test_RD 00000023
|
Tmr0 00000001
|
Tmr0 00000001
|
Tst_ExtASCII 00000027
|
Tst_ExtASCII 00000027
|
Tst_LowerCase 00000029
|
Tst_LowerCase 00000029
|
Tst_UpperCase 00000031
|
Tst_UpperCase 00000031
|
UART_BR_Div 00000008
|
UART_BR_Div 00000008
|
UART_BR_PS 00000004
|
UART_BR_PS 00000004
|
UART_CR_BAUD 00000004
|
UART_CR_BAUD 00000004
|
UART_CR_FMT 00000004
|
UART_CR_FMT 00000004
|
UART_CR_IE 00000001
|
UART_CR_IE 00000001
|
UART_CR_MD 00000002
|
UART_CR_MD 00000002
|
UART_CR_RA 00000003
|
UART_CR_RA 00000003
|
UART_CR_RTSo 00000001
|
UART_CR_RTSo 00000001
|
UART_CR_WnR 00000001
|
UART_CR_WnR 00000001
|
MPASM 5.50 M16C5X_TST4.ASM 7-28-2013 12:14:21 PAGE 7
|
MPASM 5.50 M16C5X_TST4.ASM 12-5-2013 8:25:30 PAGE 7
|
|
|
|
|
SYMBOL TABLE
|
SYMBOL TABLE
|
LABEL VALUE
|
LABEL VALUE
|
|
|
UART_RD_DI 00000008
|
UART_RD_DI 00000008
|
UART_RD_RA 00000003
|
UART_RD_RA 00000003
|
UART_RD_RERR 00000001
|
UART_RD_RERR 00000001
|
UART_RD_RRDY 00000001
|
UART_RD_RRDY 00000001
|
UART_RD_RTO 00000001
|
UART_RD_RTO 00000001
|
UART_RD_TRDY 00000001
|
UART_RD_TRDY 00000001
|
UART_RD_WnR 00000001
|
UART_RD_WnR 00000001
|
UART_SR_CTSi 00000001
|
UART_SR_CTSi 00000001
|
UART_SR_MD 00000002
|
UART_SR_MD 00000002
|
UART_SR_RA 00000003
|
UART_SR_RA 00000003
|
UART_SR_RS 00000002
|
UART_SR_RS 00000002
|
UART_SR_RTSi 00000001
|
UART_SR_RTSi 00000001
|
UART_SR_TS 00000002
|
UART_SR_TS 00000002
|
UART_SR_WnR 00000001
|
UART_SR_WnR 00000001
|
UART_SR_iRDA 00000001
|
UART_SR_iRDA 00000001
|
UART_SR_iRTO 00000001
|
UART_SR_iRTO 00000001
|
UART_SR_iTFE 00000001
|
UART_SR_iTFE 00000001
|
UART_SR_iTHE 00000001
|
UART_SR_iTHE 00000001
|
UART_TD_DO 00000008
|
UART_TD_DO 00000008
|
UART_TD_HLD 00000001
|
UART_TD_HLD 00000001
|
UART_TD_RA 00000003
|
UART_TD_RA 00000003
|
UART_TD_RFC 00000001
|
UART_TD_RFC 00000001
|
UART_TD_Rsvd 00000001
|
UART_TD_Rsvd 00000001
|
UART_TD_TFC 00000001
|
UART_TD_TFC 00000001
|
UART_TD_WnR 00000001
|
UART_TD_WnR 00000001
|
WaitLp1 00000012
|
WaitLp1 00000012
|
WaitLp2 0000001B
|
WaitLp2 0000001B
|
WaitLp3 0000001F
|
WaitLp3 0000001F
|
WaitLp4 00000042
|
WaitLp4 00000042
|
Wr_UART_TF 0000003B
|
Wr_UART_TF 0000003B
|
__16F59 00000001
|
__16F59 00000001
|
|
|
|
|
MEMORY USAGE MAP ('X' = Used, '-' = Unused)
|
MEMORY USAGE MAP ('X' = Used, '-' = Unused)
|
|
|
0000 : XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX
|
0000 : XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX
|
0040 : XXXXX----------- ---------------- ---------------- ----------------
|
0040 : XXXXX----------- ---------------- ---------------- ----------------
|
07C0 : ---------------- ---------------- ---------------- ---------------X
|
07C0 : ---------------- ---------------- ---------------- ---------------X
|
|
|
All other memory blocks unused.
|
All other memory blocks unused.
|
|
|
Program Memory Words Used: 70
|
Program Memory Words Used: 70
|
Program Memory Words Free: 1978
|
Program Memory Words Free: 1978
|
|
|
|
|
Errors : 0
|
Errors : 0
|
Warnings : 0 reported, 0 suppressed
|
Warnings : 0 reported, 0 suppressed
|
Messages : 1 reported, 0 suppressed
|
Messages : 1 reported, 0 suppressed
|
|
|
|
|