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General Description
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General Description
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-------------------
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-------------------
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This project demonstrates the use of a PIC16C5x-compatible core as an FPGA-
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This project demonstrates the use of a PIC16C5x-compatible core as an FPGA-
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based processor. The core provided is instruction set compatible, but it is
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based processor. It implements the 12-bit instruction set, the timer 0 module,
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not a cycle accurate model of any particular PIC microcomputer. It implements
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the pre-scaler, and the watchdog timer. The core provided here is compatible
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the 12-bit instruction set, the timer 0 module, the pre-scaler, and the watchdog
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with instruction set, but it is not a cycle accurate model of any particular
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timer.
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PIC microcomputer.
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As configured, the core supports single cycle (1) operation with internal
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As configured, the core supports single cycle (1) operation with internal
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block RAM serving as program memory. In addition to the block RAM program
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block RAM serving as program memory. In addition to the block RAM program
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store, a 4x clock generator and reset controller is included as part of the in
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store, a 4x clock generator and reset controller is included as part of the
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the demonstration.
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demonstration.
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Three I/O ports are supported, but they are accessed as external registers and
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Three I/O ports are supported, but they are accessed as external registers and
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buffers using a bidirectional data bus. The TRIS I/O control registers are
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buffers using a bidirectional data bus. The TRIS I/O control registers are
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similarly supported. Thus, the core's user is able to map the TRIS and I/O
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similarly supported. Thus, the core's user is able to map the TRIS and I/O
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port registers in a manner appropriate to the intended application.
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port registers in a manner appropriate to the intended application.
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Best Case Achievable: 12.381 ns (0.119 ns Setup, 0.691 ns Hold)
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Best Case Achievable: 12.381 ns (0.119 ns Setup, 0.691 ns Hold)
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Status
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Status
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------
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------
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Design and initial verification is complete. Verification using ISim, MPLAB,
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Design and verification is complete. Verification performed using ISim, MPLAB,
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and a board with an XC3S200AN-4VQG100I FPGA, various oscillators, SEEPROMs,
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and a board with an XC3S200AN-4VQG100I FPGA, various oscillators, SEEPROMs,
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and RS-232/RS-485 transceivers is underway.
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and RS-232/RS-485 transceivers.
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In circuit testing of the M16C5x soft-core microcomputer has demonstrated that
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the M16C5x can operate to **147.4560 MHz**. At this internal system clock
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frequency, a 10x multiplication of the external reference oscillator, the SPI
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shift clock divider must be set to divide the system clock by 4, which
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generates an SPI shift clock frequency of 36.864 MHz. Various combinations of
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the DCM multiplier have been generated at tested in the XC3S200A-4VQG100I
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FPGA. The following table shows the system clock frequencies tested, the SPI
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shift clock frequencies tested, and the maximum achievable standard UART bit
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rate:
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DCM Multiplier System Clock (MHz) SPI Clock (MHz) Max UART bit rate (MHz)
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4x 58.9824 29.4912 3.6864
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5x 73.7280 36.8640 0.9216
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6x 88.4736 44.2368 0.9216
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6.5x 95.8464 47.9232 0.4608
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7x 103.2192 51.6096 0.9216
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7.5x 110.5920 55.2960 0.4608
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8x 117.9648 58.9824 7.3728
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8.5x 125.3376 62.6688 0.4608
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10x 147.4560 36.8640 1.8432
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These results are only applicable to this particular configuration. The period
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constraint for the system clock is set for 12.5 ns, or 80 MHz. The
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relationship between the clock enable, 0.5 of the system clock, does not seem
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to be accomodated by the reported performance values. Further investigation is
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needed to establish if the results provided in the previous table should be
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accepted as the performance limits of the M16C5x core in this FPGA family.
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A board has been configured with an XC3S50A-4VQG100I components, and it
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operates as expected at 80 MHz. A new internal resource configuration makes
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the UART clock, Clk_UART, a fixed output of the DCM. The UART clock is fixed
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at 2x ClkIn, or as is the case in this test configuration, 29.4912 MHz.
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Testing like that performed above with the XC3S200A-4VQG100I is shown below.
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It indicates that the upper operating frequency is limited to **140.0832
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MHz**. This upper limit is most likely imposed by the reduction in routing
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resources. The utilization factor in an XC3S50A-4VQG100I FPGA is **99%**, and _~50%_
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in an XC3S200A-4VQG100I FPGA. The larger number of LUTs/Slices and routing
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resources allows Map and Place greater flexibility to satisfy the timing
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constraints.
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DCM Multiplier System Clock (MHz) SPI Clock (MHz) Max UART bit rate (MHz)
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4x 58.9824 29.4912 1.8432
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8x 117.9648 58.9824 1.8432
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8.5x 125.3376 62.6688 1.8432
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9x 132.7104 66.3552 1.8432
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9.5x 140.0832 70.0461 1.8432
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Release Notes
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Release Notes
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-------------
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-------------
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###Release 1.0
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###Release 1.0
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MHz. This rate is equivalent to the 117.9848 MHz reported above of for Release
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MHz. This rate is equivalent to the 117.9848 MHz reported above of for Release
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2.4. Some combinatorial path improvements were made to the processor core,
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2.4. Some combinatorial path improvements were made to the processor core,
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P16C5x, by using wired-OR bus connections rather than explicit multiplexers.
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P16C5x, by using wired-OR bus connections rather than explicit multiplexers.
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These improvements also provided some reductions in the resource utilization
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These improvements also provided some reductions in the resource utilization
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of the project.
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of the project.
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####Release 2.5.1
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Modified the BMM file to allow the MEM file data fields to be represented in
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natural order. In other words, unlike the previous release, the most
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significant nibble is the first (leftmost) character of each data word, and
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the least significant nibble is the last (rightmost) character in a data word.
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Also modified the utility provided that converts Intel Hex programming files
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into files compatible with the Xilinx Data2MEM utility program.
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