M16C5x Soft-Core Microcomputer
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M16C5x Soft-Core Microcomputer
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=======================
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=======================
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Copyright (C) 2013, Michael A. Morris .
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Copyright (C) 2013, Michael A. Morris .
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All Rights Reserved.
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All Rights Reserved.
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Released under LGPL.
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Released under LGPL.
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General Description
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General Description
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-------------------
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-------------------
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This project demonstrates the use of a PIC16C5x-compatible core as an FPGA-
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This project demonstrates the use of a PIC16C5x-compatible core as an FPGA-
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based processor. The core provided is instruction set compatible, but it is
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based processor. It implements the 12-bit instruction set, the timer 0 module,
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not a cycle accurate model of any particular PIC microcomputer. It implements
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the pre-scaler, and the watchdog timer. The core provided here is compatible
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the 12-bit instruction set, the timer 0 module, the pre-scaler, and the watchdog
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with instruction set, but it is not a cycle accurate model of any particular
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timer.
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PIC microcomputer.
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As configured, the core supports single cycle (1) operation with internal
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As configured, the core supports single cycle (1) operation with internal
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block RAM serving as program memory. In addition to the block RAM program
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block RAM serving as program memory. In addition to the block RAM program
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store, a 4x clock generator and reset controller is included as part of the in
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store, a 4x clock generator and reset controller is included as part of the
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the demonstration.
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demonstration.
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Three I/O ports are supported, but they are accessed as external registers and
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Three I/O ports are supported, but they are accessed as external registers and
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buffers using a bidirectional data bus. The TRIS I/O control registers are
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buffers using a bidirectional data bus. The TRIS I/O control registers are
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similarly supported. Thus, the core's user is able to map the TRIS and I/O
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similarly supported. Thus, the core's user is able to map the TRIS and I/O
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port registers in a manner appropriate to the intended application.
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port registers in a manner appropriate to the intended application.
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Read-modify-operations on the I/O ports do not generate read strobes. Read
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Read-modify-operations on the I/O ports do not generate read strobes. Read
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strobes of the three I/O ports are generated only if the ports are being read
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strobes of the three I/O ports are generated only if the ports are being read
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using MOVF xxx,0 instructions. Similarly, the write enables for the three I/O
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using MOVF xxx,0 instructions. Similarly, the write enables for the three I/O
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ports are asserted whenever the ports are updated. This occurs during MOVWF
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ports are asserted whenever the ports are updated. This occurs during MOVWF
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instructions, or during read- modify-write operations such as XORF, MOVF, etc.
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instructions, or during read- modify-write operations such as XORF, MOVF, etc.
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Implementation
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Implementation
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--------------
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--------------
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The implementation of the core provided consists of several Verilog source files
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The implementation of the core provided consists of several Verilog source files
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and memory initialization files:
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and memory initialization files:
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M16C5x.v - Top level module
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M16C5x.v - Top level module
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M16C5x_ClkGen.v - M16C5x Clock/Reset Generator
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M16C5x_ClkGen.v - M16C5x Clock/Reset Generator
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P16C5x.v - PIC16C5x-compatible processor core
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P16C5x.v - PIC16C5x-compatible processor core
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P16C5x_IDEC.v - ROM-based instruction decoder for PIC16C5x core
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P16C5x_IDEC.v - ROM-based instruction decoder for PIC16C5x core
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P16C5x_ALU.v - Arithmetic & Logic Unit for PIC16C5x core
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P16C5x_ALU.v - Arithmetic & Logic Unit for PIC16C5x core
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M16C5x_SPI.v - High-Speed, FIFO-buffered SPI Master Interface
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M16C5x_SPI.v - High-Speed, FIFO-buffered SPI Master Interface
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DPSFmnCE.v - Configurable Depth/Width LUT-based Synch FIFO
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DPSFmnCE.v - Configurable Depth/Width LUT-based Synch FIFO
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TF_Init.coe - Transmit FIFO Initialization file
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TF_Init.coe - Transmit FIFO Initialization file
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RF_Init.coe - Receive FIFO Initialization file
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RF_Init.coe - Receive FIFO Initialization file
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SPIxIF.v - Configurable Master SPI I/F with clock Generator
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SPIxIF.v - Configurable Master SPI I/F with clock Generator
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M16C5x_UART.v - UART with Serial Interface
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M16C5x_UART.v - UART with Serial Interface
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SSPx_Slv.v - SSP-compatible Slave Interface
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SSPx_Slv.v - SSP-compatible Slave Interface
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SSP_UART.v - SSP-compatible UART
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SSP_UART.v - SSP-compatible UART
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re1ce.v - Rising Edge Clock Domain Crossing Synchronizer
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re1ce.v - Rising Edge Clock Domain Crossing Synchronizer
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DPSFmnCE.v - onfigurable Depth/Width LUT-based Synch FIFO
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DPSFmnCE.v - onfigurable Depth/Width LUT-based Synch FIFO
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UART_TF.coe - UART Transmit FIFO Initialization file
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UART_TF.coe - UART Transmit FIFO Initialization file
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UART_RF.coe - UART Receive FIFO Initialization file
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UART_RF.coe - UART Receive FIFO Initialization file
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UART_BRG.v - UART Baud Rate Generator
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UART_BRG.v - UART Baud Rate Generator
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UART_TXSM.v - UART Transmit State Machine (includes SR)
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UART_TXSM.v - UART Transmit State Machine (includes SR)
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UART_RXSM.v - UART Receive State Machine (includes SR)
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UART_RXSM.v - UART Receive State Machine (includes SR)
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UART_RTO.v - UART Receive Timeout Generator
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UART_RTO.v - UART Receive Timeout Generator
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UART_INT.v - UART Interrupt Generator
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UART_INT.v - UART Interrupt Generator
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M16C5x_Test.coe - M16C5x Test Program Memory Initialization File
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M16C5x_Test.coe - M16C5x Test Program Memory Initialization File
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M16C5x_Tst2.coe - M16C5x Test #2 Program Memory Initialization File
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M16C5x_Tst2.coe - M16C5x Test #2 Program Memory Initialization File
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M16C5x_Tst3.coe - M16C5x Test #3 Program Memory Initialization File
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M16C5x_Tst3.coe - M16C5x Test #3 Program Memory Initialization File
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M16C5x_Tst4.coe - M16C5x Test #4 Program Memory Initialization File
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M16C5x_Tst4.coe - M16C5x Test #4 Program Memory Initialization File
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M16C5x.ucf - M16C5x User Constraint File
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M16C5x.ucf - M16C5x User Constraint File
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M16C5x.bmm - M16C5x Block RAM Memory Map File
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M16C5x.bmm - M16C5x Block RAM Memory Map File
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Verilog tesbench files are included for the processor core, the FIFO, and the
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Verilog tesbench files are included for the processor core, the FIFO, and the
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SPI modules.
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SPI modules.
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tb_M16C5x.v - testbench for the soft-core processor module
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tb_M16C5x.v - testbench for the soft-core processor module
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tb_P16C5x.v - testbench for the processor core module
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tb_P16C5x.v - testbench for the processor core module
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tb_DPSFmnCE.v - testbench for the LUT-based FIFO module
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tb_DPSFmnCE.v - testbench for the LUT-based FIFO module
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tb_SPIxIF.v - testbench for the SPI Master Interface module
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tb_SPIxIF.v - testbench for the SPI Master Interface module
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Also provided is the MPLAB project and the source files used to create the
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Also provided is the MPLAB project and the source files used to create the
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memory initialization files for testing the microcomputer application. These
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memory initialization files for testing the microcomputer application. These
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files are found in the MPLAB subdirectory of the Code directory.
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files are found in the MPLAB subdirectory of the Code directory.
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Finally, the configuration of the Xilinx tools used to synthesize, map, place,
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Finally, the configuration of the Xilinx tools used to synthesize, map, place,
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and route are captured in the the TCL file:
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and route are captured in the the TCL file:
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M16C5x_3S50A.tcl - TCL file for XC3S50A-4VQG100I FPGA
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M16C5x_3S50A.tcl - TCL file for XC3S50A-4VQG100I FPGA
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Run this TCL script from within the TCL console of ISE, or examine it in a
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Run this TCL script from within the TCL console of ISE, or examine it in a
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text editor, to set up the project files and to set the tools to the options
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text editor, to set up the project files and to set the tools to the options
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used to achieve the results provided here.
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used to achieve the results provided here.
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Added utility program to convert MPLAB Intel Hex programming files into MEM
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Added utility program to convert MPLAB Intel Hex programming files into MEM
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files for use with Xilinx Data2MEM utility program to speed the process of
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files for use with Xilinx Data2MEM utility program to speed the process of
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incorporating program/data/parameter data into block RAMs. TCL also
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incorporating program/data/parameter data into block RAMs. TCL also
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incorporates the process parameter changes to get the BMM file processed by
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incorporates the process parameter changes to get the BMM file processed by
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Map/PAR/Bitgen.
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Map/PAR/Bitgen.
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IH2MEM.c - Source code for Intel Hex to MEM utility
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IH2MEM.c - Source code for Intel Hex to MEM utility
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IH2MEM.exe - Windows Executable (32-bit)
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IH2MEM.exe - Windows Executable (32-bit)
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M16C5x_Tst3.mem - M16C5x Test #3 Program Memory Data2Mem File
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M16C5x_Tst3.mem - M16C5x Test #3 Program Memory Data2Mem File
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M16C5x_Tst4.mem - M16C5x Test #4 Program Memory Data2Mem File
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M16C5x_Tst4.mem - M16C5x Test #4 Program Memory Data2Mem File
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Synthesis
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Synthesis
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---------
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---------
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The primary objective of the M16C5x is to synthesize a processor core, 4kW of
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The primary objective of the M16C5x is to synthesize a processor core, 4kW of
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program memory, a buffered SPI master, and a buffered UART into a Xilinx
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program memory, a buffered SPI master, and a buffered UART into a Xilinx
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XC3S50A-4VQG100I FPGA. The present implementation includes the P16C5x core,
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XC3S50A-4VQG100I FPGA. The present implementation includes the P16C5x core,
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4kW of program memory, a dual-channel SPI Master I/F, and an SSP-compatible
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4kW of program memory, a dual-channel SPI Master I/F, and an SSP-compatible
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UART supporting baud rates from 3M bps to 1200 bps.
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UART supporting baud rates from 3M bps to 1200 bps.
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Using ISE 10.1i SP3, the implementation results for an XC3S50A-4VQ100I are as
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Using ISE 10.1i SP3, the implementation results for an XC3S50A-4VQ100I are as
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follows:
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follows:
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Number of Slice FFs: 619 of 1408 43%
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Number of Slice FFs: 619 of 1408 43%
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Number of 4-input LUTs: 1287 of 1408 92%
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Number of 4-input LUTs: 1287 of 1408 92%
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Number of Occupied Slices: 701 of 704 99%
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Number of Occupied Slices: 701 of 704 99%
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Total Number of 4-input LUTs: 1333 of 1408 94%
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Total Number of 4-input LUTs: 1333 of 1408 94%
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Logic: 1052
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Logic: 1052
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Route-Through: 46
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Route-Through: 46
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16x1 RAMs: 8
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16x1 RAMs: 8
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Dual-Port RAMs: 194
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Dual-Port RAMs: 194
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32x1 RAMs: 32
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32x1 RAMs: 32
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Shift Registers: 1
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Shift Registers: 1
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Number of BUFGMUXs: 4 of 24 16%
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Number of BUFGMUXs: 4 of 24 16%
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Number of DCMs: 1 of 2 50%
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Number of DCMs: 1 of 2 50%
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Number of RAMB16BWEs 3 of 3 100%
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Number of RAMB16BWEs 3 of 3 100%
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Best Case Achievable: 12.381 ns (0.119 ns Setup, 0.691 ns Hold)
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Best Case Achievable: 12.381 ns (0.119 ns Setup, 0.691 ns Hold)
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Status
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Status
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------
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------
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Design and initial verification is complete. Verification using ISim, MPLAB,
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Design and verification is complete. Verification performed using ISim, MPLAB,
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and a board with an XC3S200AN-4VQG100I FPGA, various oscillators, SEEPROMs,
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and a board with an XC3S200AN-4VQG100I FPGA, various oscillators, SEEPROMs,
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and RS-232/RS-485 transceivers is underway.
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and RS-232/RS-485 transceivers.
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In circuit testing of the M16C5x soft-core microcomputer has demonstrated that
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the M16C5x can operate to **147.4560 MHz**. At this internal system clock
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frequency, a 10x multiplication of the external reference oscillator, the SPI
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shift clock divider must be set to divide the system clock by 4, which
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generates an SPI shift clock frequency of 36.864 MHz. Various combinations of
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the DCM multiplier have been generated at tested in the XC3S200A-4VQG100I
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FPGA. The following table shows the system clock frequencies tested, the SPI
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shift clock frequencies tested, and the maximum achievable standard UART bit
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rate:
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DCM Multiplier System Clock (MHz) SPI Clock (MHz) Max UART bit rate (MHz)
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4x 58.9824 29.4912 3.6864
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5x 73.7280 36.8640 0.9216
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6x 88.4736 44.2368 0.9216
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6.5x 95.8464 47.9232 0.4608
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7x 103.2192 51.6096 0.9216
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7.5x 110.5920 55.2960 0.4608
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8x 117.9648 58.9824 7.3728
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8.5x 125.3376 62.6688 0.4608
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10x 147.4560 36.8640 1.8432
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These results are only applicable to this particular configuration. The period
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constraint for the system clock is set for 12.5 ns, or 80 MHz. The
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relationship between the clock enable, 0.5 of the system clock, does not seem
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to be accomodated by the reported performance values. Further investigation is
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needed to establish if the results provided in the previous table should be
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accepted as the performance limits of the M16C5x core in this FPGA family.
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A board has been configured with an XC3S50A-4VQG100I components, and it
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operates as expected at 80 MHz. A new internal resource configuration makes
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the UART clock, Clk_UART, a fixed output of the DCM. The UART clock is fixed
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at 2x ClkIn, or as is the case in this test configuration, 29.4912 MHz.
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Testing like that performed above with the XC3S200A-4VQG100I is shown below.
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It indicates that the upper operating frequency is limited to **140.0832
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MHz**. This upper limit is most likely imposed by the reduction in routing
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resources. The utilization factor in an XC3S50A-4VQG100I FPGA is **99%**, and _~50%_
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in an XC3S200A-4VQG100I FPGA. The larger number of LUTs/Slices and routing
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resources allows Map and Place greater flexibility to satisfy the timing
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constraints.
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DCM Multiplier System Clock (MHz) SPI Clock (MHz) Max UART bit rate (MHz)
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4x 58.9824 29.4912 1.8432
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8x 117.9648 58.9824 1.8432
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8.5x 125.3376 62.6688 1.8432
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9x 132.7104 66.3552 1.8432
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9.5x 140.0832 70.0461 1.8432
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Release Notes
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Release Notes
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-------------
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-------------
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###Release 1.0
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###Release 1.0
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In this release, the M16C5x has been synthesized, mapped, placed, routed, and
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In this release, the M16C5x has been synthesized, mapped, placed, routed, and
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used to configure an FPGA. The FPGA used for this initial test of the M16C5x
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used to configure an FPGA. The FPGA used for this initial test of the M16C5x
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was the XC3S200A-4VQG100I FPGA. The test program provided demonstrated that
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was the XC3S200A-4VQG100I FPGA. The test program provided demonstrated that
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the M16C5x was executing the program in the same manner as simulated with the
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the M16C5x was executing the program in the same manner as simulated with the
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MPLAB simulator.
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MPLAB simulator.
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Using an external 14.7456 MHz oscillator, selected for use for use with the
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Using an external 14.7456 MHz oscillator, selected for use for use with the
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UART, square waves were generated by the core to illuminate external LEDs
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UART, square waves were generated by the core to illuminate external LEDs
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using the upper 6 bits of PortA. The square waves have the appropriate ratios,
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using the upper 6 bits of PortA. The square waves have the appropriate ratios,
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and the frequency of the fastest LED drive signal is ~4.753kHz.
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and the frequency of the fastest LED drive signal is ~4.753kHz.
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The clock generator multiplies the input frequency to 58.9824 MHz which
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The clock generator multiplies the input frequency to 58.9824 MHz which
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results in an effective instruction frequency of 29.4912 MHz because of the
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results in an effective instruction frequency of 29.4912 MHz because of the
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two cycle nature of the core. The instruction loop is essentially 8*(*+3*256),
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two cycle nature of the core. The instruction loop is essentially 8*(*+3*256),
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which equals 6208 cycles per LED toggle. The measured toggle frequency of the
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which equals 6208 cycles per LED toggle. The measured toggle frequency of the
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fastest LED is approximately equal to 29.4912 MHz / 6208, or 4.750 kHz.
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fastest LED is approximately equal to 29.4912 MHz / 6208, or 4.750 kHz.
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Work will continue to verify the testbench results with the FPGA. The next
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Work will continue to verify the testbench results with the FPGA. The next
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release should include the UART, and test the ability of the core to
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release should include the UART, and test the ability of the core to
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send/receive data using the FIFOs at rates of 115,200 baud or greater.
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send/receive data using the FIFOs at rates of 115,200 baud or greater.
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###Release 2.0
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###Release 2.0
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In this release, the UART has been addded. An update has been made to the SPI
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In this release, the UART has been addded. An update has been made to the SPI
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I/F Master function; update correct fault with the framing of SPI Mode 3
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I/F Master function; update correct fault with the framing of SPI Mode 3
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frames with shift lengths greater than 1 byte. A correction, not fully tested
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frames with shift lengths greater than 1 byte. A correction, not fully tested
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or verified, was made to the P16C5x core to correct anomalous behavior for
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or verified, was made to the P16C5x core to correct anomalous behavior for
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BTFSC/BTFSS instructions.
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BTFSC/BTFSS instructions.
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UART integrated with the Release 1.0 core. Verification of the integrated
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UART integrated with the Release 1.0 core. Verification of the integrated
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interface is underway.
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interface is underway.
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###Release 2.1
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###Release 2.1
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Testing with an M16C5x core processor program assembled using
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Testing with an M16C5x core processor program assembled using
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MPLAB and ISIM showed that polling of the UART status register to determine
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MPLAB and ISIM showed that polling of the UART status register to determine
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whether the transmit FIFO was empty or not (using the iTFE interrupt flag)
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whether the transmit FIFO was empty or not (using the iTFE interrupt flag)
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would clear the generated interrupt flags before they had actually been
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would clear the generated interrupt flags before they had actually been
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captured and shifted in the SSP response to the core.
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captured and shifted in the SSP response to the core.
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This indicated a clock domain crossing issue in the interrupt clearing logic.
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This indicated a clock domain crossing issue in the interrupt clearing logic.
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This release fixes that issue. Previous use of the UART does not poll the USR,
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This release fixes that issue. Previous use of the UART does not poll the USR,
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so this problem does not manisfest itself in a reasonable amount of time, if
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so this problem does not manisfest itself in a reasonable amount of time, if
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ever. In other words, the synchronization fault has been present all along in
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ever. In other words, the synchronization fault has been present all along in
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the implementation, but the module's usage in the application (or testbench)
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the implementation, but the module's usage in the application (or testbench)
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did not present the conditions under which the fault manifests.
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did not present the conditions under which the fault manifests.
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The correction required registering the USR data on the SSP clock domain, and
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The correction required registering the USR data on the SSP clock domain, and
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qualifying the clearing of the interrupt flags on the basis of whether the
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qualifying the clearing of the interrupt flags on the basis of whether the
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flag is set in both domains when the USR is read. The addition of the register
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flag is set in both domains when the USR is read. The addition of the register
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reduced the logic utilization, and only a small additonal time delay was
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reduced the logic utilization, and only a small additonal time delay was
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incurred. The resulting design is still able to fit into a Spartan 3A XC3S50A-
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incurred. The resulting design is still able to fit into a Spartan 3A XC3S50A-
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4VQG100I FPGA.
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4VQG100I FPGA.
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Modified the UART Baud Rate Generator. Removed the fixed 16x12 ROM that
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Modified the UART Baud Rate Generator. Removed the fixed 16x12 ROM that
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provided the pre-scaler and divider constants for a fixed set of 16 baud
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provided the pre-scaler and divider constants for a fixed set of 16 baud
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rates. Added a 12-bit, write-only register, BRR - Baud Rate Register, that can
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rates. Added a 12-bit, write-only register, BRR - Baud Rate Register, that can
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be used to set the baud rate from 1/16 of the processor clock. With a
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be used to set the baud rate from 1/16 of the processor clock. With a
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58.9824 MHz oscillator, the baud rate can range from 3.6864Mbps down to 900 bps.
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58.9824 MHz oscillator, the baud rate can range from 3.6864Mbps down to 900 bps.
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Set the default baud rate to 9600 for a 58.9824 MHz UART clock.
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Set the default baud rate to 9600 for a 58.9824 MHz UART clock.
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Utilization for a XC3S50A-4VQG100I FPGA is 100%. The 128 byte LUT-based
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Utilization for a XC3S50A-4VQG100I FPGA is 100%. The 128 byte LUT-based
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receive FIFO can be reduced to accomodate some additional functions. Synthesis
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receive FIFO can be reduced to accomodate some additional functions. Synthesis
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and MAP/PAR able to implement the design. There is also some place holder
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and MAP/PAR able to implement the design. There is also some place holder
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logic that can be used for other purposes.
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logic that can be used for other purposes.
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###Release 2.2
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###Release 2.2
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Updated the soft-core so as to be able to parameterize the microcontroller
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Updated the soft-core so as to be able to parameterize the microcontroller
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from the top module. Changed the frequency multiplication from 4 to 5 in order
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from the top module. Changed the frequency multiplication from 4 to 5 in order
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to test operation at the frequency which the UCF constrains Map/PAR tools. The
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to test operation at the frequency which the UCF constrains Map/PAR tools. The
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input clock is driven by a 14.7456 MHz oscillator, and the clock multiplier
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input clock is driven by a 14.7456 MHz oscillator, and the clock multiplier
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(DCM) generates **73.7280 MHz**. The default baud rate, 9600, required that the
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(DCM) generates **73.7280 MHz**. The default baud rate, 9600, required that the
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default settings be adjusted. All other parameters remain the same.
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default settings be adjusted. All other parameters remain the same.
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|
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Also added a Block RAM Memory Map file to the project. Utilized Xilinx's
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Also added a Block RAM Memory Map file to the project. Utilized Xilinx's
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Data2MEM tool to insert modified program contents into the affected Block RAMs
|
Data2MEM tool to insert modified program contents into the affected Block RAMs
|
using MEM files dereived from standard MPLAB outputs. Tutorial on this subject
|
using MEM files dereived from standard MPLAB outputs. Tutorial on this subject
|
is being prepared and will be released on an associated Wiki soon.
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is being prepared and will be released on an associated Wiki soon.
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|
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###Release 2.3
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###Release 2.3
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Updated the soft-core microcomputer. Fixed the UART clock, Clk_UART, to twice
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Updated the soft-core microcomputer. Fixed the UART clock, Clk_UART, to twice
|
the input frequency. This means that the UART operates with a fixed reference
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the input frequency. This means that the UART operates with a fixed reference
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frequency unlike Release 2.2 where Clk_UART was set to the system clock
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frequency unlike Release 2.2 where Clk_UART was set to the system clock
|
frequency.
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frequency.
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|
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Also added asynchronous resets to several registers in the UART so that it
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Also added asynchronous resets to several registers in the UART so that it
|
would simulate correcly with ISim. Direct control of the UART prescaler and
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would simulate correcly with ISim. Direct control of the UART prescaler and
|
divider was previously untested using the simulation. With that change to the
|
divider was previously untested using the simulation. With that change to the
|
baud rate generator made to UART, the reset/power-on values of these two logic
|
baud rate generator made to UART, the reset/power-on values of these two logic
|
functions are unknown. The unknowns, "X", propagate through the baud rate
|
functions are unknown. The unknowns, "X", propagate through the baud rate
|
generator and prevent the simulator from resolving the state of the internal
|
generator and prevent the simulator from resolving the state of the internal
|
baud rate clock of the UART. Thus, although the rest of circuits simulate as
|
baud rate clock of the UART. Thus, although the rest of circuits simulate as
|
expected, the transmit shift register never shifts because there's an
|
expected, the transmit shift register never shifts because there's an
|
"unknown" signal level applied on the bit clock.
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"unknown" signal level applied on the bit clock.
|
|
|
###Release 2.4
|
###Release 2.4
|
|
|
Polling the UART's Receive Data Register (RDR) uncovered a race condition like
|
Polling the UART's Receive Data Register (RDR) uncovered a race condition like
|
that previously found and corrected in regards to polling the UART Status
|
that previously found and corrected in regards to polling the UART Status
|
Register (USR). Correction required registering the RDR in the SCK clock
|
Register (USR). Correction required registering the RDR in the SCK clock
|
domain, and qualifying the read enable pulse for the receive FIFO so that it
|
domain, and qualifying the read enable pulse for the receive FIFO so that it
|
is only generated if the Receive Rdy flag is present in the SCK clock domain.
|
is only generated if the Receive Rdy flag is present in the SCK clock domain.
|
Otherwise, the Receive FIFO is not read which prevents the inadvertent
|
Otherwise, the Receive FIFO is not read which prevents the inadvertent
|
clearing of the FIFO empty flag.
|
clearing of the FIFO empty flag.
|
|
|
Test Program 4, M16C5x_Tst4.asm, is used to test the receive signal path.
|
Test Program 4, M16C5x_Tst4.asm, is used to test the receive signal path.
|
Hyperterminal and Tera Term were used to sent (without local echo) several
|
Hyperterminal and Tera Term were used to sent (without local echo) several
|
large text files through the M16C5x UART. The test program polls the RDR, and
|
large text files through the M16C5x UART. The test program polls the RDR, and
|
if a character is received without error, then upper case are converted to
|
if a character is received without error, then upper case are converted to
|
lower case characters, and vice-versa. Using a Keyspan Quad Port USB serial
|
lower case characters, and vice-versa. Using a Keyspan Quad Port USB serial
|
port adapter, characters were sent to the M16C5x at a rate of 921.6k baud, the
|
port adapter, characters were sent to the M16C5x at a rate of 921.6k baud, the
|
highest programmable baud rate supported by the Keyspan device. The echo back
|
highest programmable baud rate supported by the Keyspan device. The echo back
|
to terminal emulator appeared to be without error. (**Note:** _the two wire
|
to terminal emulator appeared to be without error. (**Note:** _the two wire
|
RS-232 mode of the UART was used for this test. The ADM3232 charge-pump RS-232
|
RS-232 mode of the UART was used for this test. The ADM3232 charge-pump RS-232
|
transceiver appeared to work well at this frequency. Som slew rate limiting is
|
transceiver appeared to work well at this frequency. Som slew rate limiting is
|
visible on an O-scope, but it appears to be tolerable. These tests were
|
visible on an O-scope, but it appears to be tolerable. These tests were
|
conducted while the core was operating at **117.9648 MHz**._)
|
conducted while the core was operating at **117.9648 MHz**._)
|
|
|
This release is expected to be the last public release of this soft-core
|
This release is expected to be the last public release of this soft-core
|
microcomputer. The released core and peripherals are sufficient to demonstrate
|
microcomputer. The released core and peripherals are sufficient to demonstrate
|
a non-trivial FPGA implementation of a soft-core microcomputer. Further
|
a non-trivial FPGA implementation of a soft-core microcomputer. Further
|
developments will be focused on improving access to the internal block RAMs,
|
developments will be focused on improving access to the internal block RAMs,
|
and improving the I/O capabilities of the release core.
|
and improving the I/O capabilities of the release core.
|
|
|
###Release 2.5
|
###Release 2.5
|
|
|
Converted the core to operate in a single cycle mode with the block RAM
|
Converted the core to operate in a single cycle mode with the block RAM
|
memories of the FPGA. Operating frequency, in a -4 Spartan 3A FPGA, is 60+
|
memories of the FPGA. Operating frequency, in a -4 Spartan 3A FPGA, is 60+
|
MHz. This rate is equivalent to the 117.9848 MHz reported above of for Release
|
MHz. This rate is equivalent to the 117.9848 MHz reported above of for Release
|
2.4. Some combinatorial path improvements were made to the processor core,
|
2.4. Some combinatorial path improvements were made to the processor core,
|
P16C5x, by using wired-OR bus connections rather than explicit multiplexers.
|
P16C5x, by using wired-OR bus connections rather than explicit multiplexers.
|
These improvements also provided some reductions in the resource utilization
|
These improvements also provided some reductions in the resource utilization
|
of the project.
|
of the project.
|
|
|
|
####Release 2.5.1
|
|
|
|
Modified the BMM file to allow the MEM file data fields to be represented in
|
|
natural order. In other words, unlike the previous release, the most
|
|
significant nibble is the first (leftmost) character of each data word, and
|
|
the least significant nibble is the last (rightmost) character in a data word.
|
|
Also modified the utility provided that converts Intel Hex programming files
|
|
into files compatible with the Xilinx Data2MEM utility program.
|
|
|