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[/] [m1_core/] [trunk/] [hdl/] [rtl/] [m1_core/] [m1_mmu.v] - Diff between revs 54 and 64

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/*
/*
 * Simply RISC M1 Memory Management Unit
 * M1 Memory Management Unit
 *
 *
 * This block converts Harvard architecture requests to access the
 * This block converts Harvard architecture requests to access the
 * small internal prefetch buffer, and just in case the external
 * small internal prefetch buffer, and just in case the external
 * Wishbone bus.
 * Wishbone bus.
 * Memory size is 256 word * 4 byte = 1024 byte,
 * Memory size is 256 word * 4 byte = 1024 byte,

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