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/*
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/*
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* Simply RISC M1 Memory Management Unit
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* M1 Memory Management Unit
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*
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*
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* This block converts Harvard architecture requests to access the
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* This block converts Harvard architecture requests to access the
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* small internal prefetch buffer, and just in case the external
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* small internal prefetch buffer, and just in case the external
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* Wishbone bus.
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* Wishbone bus.
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* Memory size is 256 word * 4 byte = 1024 byte,
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* Memory size is 256 word * 4 byte = 1024 byte,
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