/*
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/*
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* Simply RISC M1 Core System for Xilinx Spartan-3E 500 Starter Kit
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* M1 Core System for Xilinx Spartan-3E 500 Starter Kit
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*/
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*/
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`include "ddr_include.v"
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`include "ddr_include.v"
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module spartan3esk_top (
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module spartan3esk_top (
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// System
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// System
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input sys_clock_i,
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input sys_clock_i,
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input sys_reset_i,
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input sys_reset_i,
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// VGA Port
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// VGA Port
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output vga_rgb_r_o,
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output vga_rgb_r_o,
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output vga_rgb_g_o,
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output vga_rgb_g_o,
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output vga_rgb_b_o,
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output vga_rgb_b_o,
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output vga_hsync_o,
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output vga_hsync_o,
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output vga_vsync_o,
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output vga_vsync_o,
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// PS/2 Keyboard interface
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// PS/2 Keyboard interface
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inout ps2_keyboard_clock_io,
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inout ps2_keyboard_clock_io,
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inout ps2_keyboard_data_io,
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inout ps2_keyboard_data_io,
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// DDR Port
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// DDR Port
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output ddr_clk,
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output ddr_clk,
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output ddr_clk_n,
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output ddr_clk_n,
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input ddr_clk_fb,
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input ddr_clk_fb,
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output ddr_ras_n,
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output ddr_ras_n,
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output ddr_cas_n,
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output ddr_cas_n,
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output ddr_we_n,
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output ddr_we_n,
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output ddr_cke,
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output ddr_cke,
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output ddr_cs_n,
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output ddr_cs_n,
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output[`A_RNG] ddr_a,
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output[`A_RNG] ddr_a,
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output[`BA_RNG] ddr_ba,
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output[`BA_RNG] ddr_ba,
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inout[`DQ_RNG] ddr_dq,
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inout[`DQ_RNG] ddr_dq,
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inout[`DQS_RNG] ddr_dqs,
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inout[`DQS_RNG] ddr_dqs,
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output[`DM_RNG] ddr_dm
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output[`DM_RNG] ddr_dm
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);
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);
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/*
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/*
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* Wires
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* Wires
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*/
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*/
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// Interrupts
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// Interrupts
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wire sys_irq;
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wire sys_irq;
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wire[31:0] sys_irqs;
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wire[31:0] sys_irqs;
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assign sys_irqs[31:1] = 31'h00000000;
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assign sys_irqs[31:1] = 31'h00000000;
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// Rotary interface
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// Rotary interface
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wire[2:0] rot = 3'b000;
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wire[2:0] rot = 3'b000;
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// PS/2 Keyboard interface
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// PS/2 Keyboard interface
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wire ps2_keyboard_clock_i;
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wire ps2_keyboard_clock_i;
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wire ps2_keyboard_data_i;
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wire ps2_keyboard_data_i;
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wire ps2_keyboard_clock_o;
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wire ps2_keyboard_clock_o;
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wire ps2_keyboard_data_o;
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wire ps2_keyboard_data_o;
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wire ps2_keyboard_clock_padoe_o;
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wire ps2_keyboard_clock_padoe_o;
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wire ps2_keyboard_data_padoe_o;
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wire ps2_keyboard_data_padoe_o;
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assign ps2_keyboard_clock_io = (ps2_keyboard_clock_padoe_o ? ps2_keyboard_clock_o : 1'bZ);
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assign ps2_keyboard_clock_io = (ps2_keyboard_clock_padoe_o ? ps2_keyboard_clock_o : 1'bZ);
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assign ps2_keyboard_data_io = (ps2_keyboard_data_padoe_o ? ps2_keyboard_data_o : 1'bZ);
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assign ps2_keyboard_data_io = (ps2_keyboard_data_padoe_o ? ps2_keyboard_data_o : 1'bZ);
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// Wishbone interface
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// Wishbone interface
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wire wb_cyc_core, wb_cyc_intc, wb_cyc_text, wb_cyc_ps2, wb_cyc_ddr;
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wire wb_cyc_core, wb_cyc_intc, wb_cyc_text, wb_cyc_ps2, wb_cyc_ddr;
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wire wb_stb_core, wb_stb_intc, wb_stb_text, wb_stb_ps2, wb_stb_ddr;
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wire wb_stb_core, wb_stb_intc, wb_stb_text, wb_stb_ps2, wb_stb_ddr;
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wire wb_we_core, wb_we_intc, wb_we_text, wb_we_ps2, wb_we_ddr;
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wire wb_we_core, wb_we_intc, wb_we_text, wb_we_ps2, wb_we_ddr;
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wire[31:0] wb_adr_core, wb_adr_intc, wb_adr_text, wb_adr_ps2, wb_adr_ddr;
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wire[31:0] wb_adr_core, wb_adr_intc, wb_adr_text, wb_adr_ps2, wb_adr_ddr;
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wire[31:0] wb_wdat_core, wb_wdat_intc, wb_wdat_text, wb_wdat_ps2, wb_wdat_ddr;
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wire[31:0] wb_wdat_core, wb_wdat_intc, wb_wdat_text, wb_wdat_ps2, wb_wdat_ddr;
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wire[3:0] wb_sel_core, wb_sel_intc, wb_sel_text, wb_sel_ps2, wb_sel_ddr;
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wire[3:0] wb_sel_core, wb_sel_intc, wb_sel_text, wb_sel_ps2, wb_sel_ddr;
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wire wb_ack_core, wb_ack_intc, wb_ack_text, wb_ack_ps2, wb_ack_ddr;
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wire wb_ack_core, wb_ack_intc, wb_ack_text, wb_ack_ps2, wb_ack_ddr;
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wire[31:0] wb_rdat_core, wb_rdat_intc, wb_rdat_text, wb_rdat_ps2, wb_rdat_ddr;
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wire[31:0] wb_rdat_core, wb_rdat_intc, wb_rdat_text, wb_rdat_ps2, wb_rdat_ddr;
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// The most significant byte of the address is used to select the destination
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// The most significant byte of the address is used to select the destination
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wire request_to_ddr = (wb_stb_core && wb_cyc_core && wb_adr_core[31:24]==8'h00);
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wire request_to_ddr = (wb_stb_core && wb_cyc_core && wb_adr_core[31:24]==8'h00);
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wire request_to_intc = (wb_stb_core && wb_cyc_core && wb_adr_core[31:24]==8'hF8);
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wire request_to_intc = (wb_stb_core && wb_cyc_core && wb_adr_core[31:24]==8'hF8);
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wire request_to_text = (wb_stb_core && wb_cyc_core && wb_adr_core[31:24]==8'hFA);
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wire request_to_text = (wb_stb_core && wb_cyc_core && wb_adr_core[31:24]==8'hFA);
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wire request_to_ps2 = (wb_stb_core && wb_cyc_core && wb_adr_core[31:24]==8'hFB);
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wire request_to_ps2 = (wb_stb_core && wb_cyc_core && wb_adr_core[31:24]==8'hFB);
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// Select outputs connected to M1 Core inputs
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// Select outputs connected to M1 Core inputs
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assign wb_ack_core = (request_to_ddr ? wb_ack_ddr :
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assign wb_ack_core = (request_to_ddr ? wb_ack_ddr :
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(request_to_intc ? wb_ack_intc :
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(request_to_intc ? wb_ack_intc :
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(request_to_text ? wb_ack_text : wb_ack_ps2) ) );
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(request_to_text ? wb_ack_text : wb_ack_ps2) ) );
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assign wb_rdat_core = (request_to_ddr ? wb_rdat_ddr :
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assign wb_rdat_core = (request_to_ddr ? wb_rdat_ddr :
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(request_to_intc ? wb_rdat_intc :
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(request_to_intc ? wb_rdat_intc :
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(request_to_text ? wb_rdat_text : wb_rdat_ps2) ) );
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(request_to_text ? wb_rdat_text : wb_rdat_ps2) ) );
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// Select outputs connected to Interrupt Controller inputs
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// Select outputs connected to Interrupt Controller inputs
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assign wb_cyc_intc = (request_to_intc ? wb_cyc_core : 1'b0);
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assign wb_cyc_intc = (request_to_intc ? wb_cyc_core : 1'b0);
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assign wb_stb_intc = (request_to_intc ? wb_stb_core : 1'b0);
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assign wb_stb_intc = (request_to_intc ? wb_stb_core : 1'b0);
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assign wb_adr_intc = (request_to_intc ? wb_adr_core : 32'h00000000);
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assign wb_adr_intc = (request_to_intc ? wb_adr_core : 32'h00000000);
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assign wb_we_intc = (request_to_intc ? wb_we_core : 1'b0);
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assign wb_we_intc = (request_to_intc ? wb_we_core : 1'b0);
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assign wb_sel_intc = (request_to_intc ? wb_sel_core : 4'b0000);
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assign wb_sel_intc = (request_to_intc ? wb_sel_core : 4'b0000);
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assign wb_wdat_intc = (request_to_intc ? wb_wdat_core : 32'h00000000);
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assign wb_wdat_intc = (request_to_intc ? wb_wdat_core : 32'h00000000);
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// Select outputs connected to Text-only VGA Controller inputs
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// Select outputs connected to Text-only VGA Controller inputs
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assign wb_cyc_text = (request_to_text ? wb_cyc_core : 1'b0);
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assign wb_cyc_text = (request_to_text ? wb_cyc_core : 1'b0);
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assign wb_stb_text = (request_to_text ? wb_stb_core : 1'b0);
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assign wb_stb_text = (request_to_text ? wb_stb_core : 1'b0);
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assign wb_adr_text = (request_to_text ? wb_adr_core : 32'h00000000);
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assign wb_adr_text = (request_to_text ? wb_adr_core : 32'h00000000);
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assign wb_we_text = (request_to_text ? wb_we_core : 1'b0);
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assign wb_we_text = (request_to_text ? wb_we_core : 1'b0);
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assign wb_sel_text = (request_to_text ? wb_sel_core : 4'b0000);
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assign wb_sel_text = (request_to_text ? wb_sel_core : 4'b0000);
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assign wb_wdat_text = (request_to_text ? wb_wdat_core : 32'h00000000);
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assign wb_wdat_text = (request_to_text ? wb_wdat_core : 32'h00000000);
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// Select outputs connected to PS/2 Keyboard Interface inputs
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// Select outputs connected to PS/2 Keyboard Interface inputs
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assign wb_cyc_ps2 = (request_to_ps2 ? wb_cyc_core : 1'b0);
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assign wb_cyc_ps2 = (request_to_ps2 ? wb_cyc_core : 1'b0);
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assign wb_stb_ps2 = (request_to_ps2 ? wb_stb_core : 1'b0);
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assign wb_stb_ps2 = (request_to_ps2 ? wb_stb_core : 1'b0);
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assign wb_adr_ps2 = (request_to_ps2 ? wb_adr_core : 32'h00000000);
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assign wb_adr_ps2 = (request_to_ps2 ? wb_adr_core : 32'h00000000);
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assign wb_we_ps2 = (request_to_ps2 ? wb_we_core : 1'b0);
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assign wb_we_ps2 = (request_to_ps2 ? wb_we_core : 1'b0);
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assign wb_sel_ps2 = (request_to_ps2 ? wb_sel_core : 4'b0000);
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assign wb_sel_ps2 = (request_to_ps2 ? wb_sel_core : 4'b0000);
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assign wb_wdat_ps2 = (request_to_ps2 ? wb_wdat_core : 32'h00000000);
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assign wb_wdat_ps2 = (request_to_ps2 ? wb_wdat_core : 32'h00000000);
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// Select outputs connected to DDR Controller inputs
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// Select outputs connected to DDR Controller inputs
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assign wb_cyc_ddr = (request_to_ddr ? wb_cyc_core : 1'b0);
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assign wb_cyc_ddr = (request_to_ddr ? wb_cyc_core : 1'b0);
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assign wb_stb_ddr = (request_to_ddr ? wb_stb_core : 1'b0);
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assign wb_stb_ddr = (request_to_ddr ? wb_stb_core : 1'b0);
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assign wb_adr_ddr = (request_to_ddr ? wb_adr_core : 32'h00000000);
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assign wb_adr_ddr = (request_to_ddr ? wb_adr_core : 32'h00000000);
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assign wb_we_ddr = (request_to_ddr ? wb_we_core : 1'b0);
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assign wb_we_ddr = (request_to_ddr ? wb_we_core : 1'b0);
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assign wb_sel_ddr = (request_to_ddr ? wb_sel_core : 4'b0000);
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assign wb_sel_ddr = (request_to_ddr ? wb_sel_core : 4'b0000);
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assign wb_wdat_ddr = (request_to_ddr ? wb_wdat_core : 32'h00000000);
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assign wb_wdat_ddr = (request_to_ddr ? wb_wdat_core : 32'h00000000);
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/*
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/*
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* Module instances
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* Module instances
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*/
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*/
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// M1 Core
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// M1 Core
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m1_core m1_core_0 (
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m1_core m1_core_0 (
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// System
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// System
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.sys_clock_i(sys_clock_i),
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.sys_clock_i(sys_clock_i),
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.sys_reset_i(sys_reset_i),
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.sys_reset_i(sys_reset_i),
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.sys_irq_i(sys_irq),
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.sys_irq_i(sys_irq),
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// Wishbone master interface
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// Wishbone master interface
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.wb_cyc_o(wb_cyc_core),
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.wb_cyc_o(wb_cyc_core),
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.wb_stb_o(wb_stb_core),
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.wb_stb_o(wb_stb_core),
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.wb_we_o(wb_we_core),
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.wb_we_o(wb_we_core),
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.wb_sel_o(wb_sel_core),
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.wb_sel_o(wb_sel_core),
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.wb_adr_o(wb_adr_core),
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.wb_adr_o(wb_adr_core),
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.wb_dat_o(wb_wdat_core),
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.wb_dat_o(wb_wdat_core),
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.wb_ack_i(wb_ack_core),
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.wb_ack_i(wb_ack_core),
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.wb_dat_i(wb_rdat_core)
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.wb_dat_i(wb_rdat_core)
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);
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);
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// Interrupt Controller
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// Interrupt Controller
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wb_int_ctrl wb_int_ctrl_0 (
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wb_int_ctrl wb_int_ctrl_0 (
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// System
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// System
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.sys_clock_i(sys_clock_i),
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.sys_clock_i(sys_clock_i),
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.sys_reset_i(sys_reset_i),
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.sys_reset_i(sys_reset_i),
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// Interrupts
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// Interrupts
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.sys_irqs_i(sys_irqs),
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.sys_irqs_i(sys_irqs),
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.sys_irq_o(sys_irq),
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.sys_irq_o(sys_irq),
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// Wishbone slave interface
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// Wishbone slave interface
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.wb_cyc_i(wb_cyc_intc),
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.wb_cyc_i(wb_cyc_intc),
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.wb_stb_i(wb_stb_intc),
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.wb_stb_i(wb_stb_intc),
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.wb_adr_i(wb_adr_intc),
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.wb_adr_i(wb_adr_intc),
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.wb_we_i(wb_we_intc),
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.wb_we_i(wb_we_intc),
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.wb_sel_i(wb_sel_intc),
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.wb_sel_i(wb_sel_intc),
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.wb_dat_i(wb_wdat_intc),
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.wb_dat_i(wb_wdat_intc),
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.wb_ack_o(wb_ack_intc),
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.wb_ack_o(wb_ack_intc),
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.wb_dat_o(wb_rdat_intc)
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.wb_dat_o(wb_rdat_intc)
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);
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);
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// Text-only VGA Controller
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// Text-only VGA Controller
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wb_text_vga wb_text_vga_0 (
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wb_text_vga wb_text_vga_0 (
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// System
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// System
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.sys_clock_i(sys_clock_i),
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.sys_clock_i(sys_clock_i),
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.sys_reset_i(sys_reset_i),
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.sys_reset_i(sys_reset_i),
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// Wishbone slave interface
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// Wishbone slave interface
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.wb_cyc_i(wb_cyc_text),
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.wb_cyc_i(wb_cyc_text),
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.wb_stb_i(wb_stb_text),
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.wb_stb_i(wb_stb_text),
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.wb_adr_i(wb_adr_text),
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.wb_adr_i(wb_adr_text),
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.wb_we_i(wb_we_text),
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.wb_we_i(wb_we_text),
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.wb_sel_i(wb_sel_text),
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.wb_sel_i(wb_sel_text),
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.wb_dat_i(wb_wdat_text),
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.wb_dat_i(wb_wdat_text),
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.wb_ack_o(wb_ack_text),
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.wb_ack_o(wb_ack_text),
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.wb_dat_o(wb_rdat_text),
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.wb_dat_o(wb_rdat_text),
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// VGA Port
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// VGA Port
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.vga_rgb_r_o(vga_rgb_r_o),
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.vga_rgb_r_o(vga_rgb_r_o),
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.vga_rgb_g_o(vga_rgb_g_o),
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.vga_rgb_g_o(vga_rgb_g_o),
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.vga_rgb_b_o(vga_rgb_b_o),
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.vga_rgb_b_o(vga_rgb_b_o),
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.vga_hsync_o(vga_hsync_o),
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.vga_hsync_o(vga_hsync_o),
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.vga_vsync_o(vga_vsync_o)
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.vga_vsync_o(vga_vsync_o)
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);
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);
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// PS/2 Keyboard Interface
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// PS/2 Keyboard Interface
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ps2_top wb_ps2_keyboard_0
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ps2_top wb_ps2_keyboard_0
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(
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(
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// System
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// System
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.wb_clk_i(sys_clock_i),
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.wb_clk_i(sys_clock_i),
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.wb_rst_i(sys_reset_i),
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.wb_rst_i(sys_reset_i),
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// Wishbone slave interface
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// Wishbone slave interface
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.wb_cyc_i(wb_cyc_ps2),
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.wb_cyc_i(wb_cyc_ps2),
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.wb_stb_i(wb_stb_ps2),
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.wb_stb_i(wb_stb_ps2),
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.wb_we_i(wb_we_ps2),
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.wb_we_i(wb_we_ps2),
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.wb_sel_i(wb_sel_ps2),
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.wb_sel_i(wb_sel_ps2),
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.wb_adr_i(wb_adr_ps2[3:0]),
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.wb_adr_i(wb_adr_ps2[3:0]),
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.wb_dat_i(wb_wdat_ps2),
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.wb_dat_i(wb_wdat_ps2),
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.wb_dat_o(wb_rdat_ps2),
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.wb_dat_o(wb_rdat_ps2),
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.wb_ack_o(wb_ack_ps2),
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.wb_ack_o(wb_ack_ps2),
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// Interrupt
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// Interrupt
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.wb_int_o(sys_irqs[0]),
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.wb_int_o(sys_irqs[0]),
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// PS/2 Keyboard Port
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// PS/2 Keyboard Port
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.ps2_kbd_clk_pad_i(ps2_keyboard_clock_i),
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.ps2_kbd_clk_pad_i(ps2_keyboard_clock_i),
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.ps2_kbd_data_pad_i(ps2_keyboard_data_i),
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.ps2_kbd_data_pad_i(ps2_keyboard_data_i),
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.ps2_kbd_clk_pad_o(ps2_keyboard_clock_o),
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.ps2_kbd_clk_pad_o(ps2_keyboard_clock_o),
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.ps2_kbd_data_pad_o(ps2_keyboard_data_o),
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.ps2_kbd_data_pad_o(ps2_keyboard_data_o),
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.ps2_kbd_clk_pad_oe_o(ps2_keyboard_clock_padoe_o),
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.ps2_kbd_clk_pad_oe_o(ps2_keyboard_clock_padoe_o),
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.ps2_kbd_data_pad_oe_o(ps2_keyboard_data_padoe_o)
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.ps2_kbd_data_pad_oe_o(ps2_keyboard_data_padoe_o)
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);
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);
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// DDR Controller
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// DDR Controller
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wb_ddr wb_ddr_0 (
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wb_ddr wb_ddr_0 (
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// System
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// System
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.clk(sys_clock_i),
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.clk(sys_clock_i),
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.reset(sys_reset_i),
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.reset(sys_reset_i),
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// DDR Port
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// DDR Port
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.ddr_clk(ddr_clk),
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.ddr_clk(ddr_clk),
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.ddr_clk_n(ddr_clk_n),
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.ddr_clk_n(ddr_clk_n),
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.ddr_clk_fb(ddr_clk_fb),
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.ddr_clk_fb(ddr_clk_fb),
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.ddr_ras_n(ddr_ras_n),
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.ddr_ras_n(ddr_ras_n),
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.ddr_cas_n(ddr_cas_n),
|
.ddr_cas_n(ddr_cas_n),
|
.ddr_we_n(ddr_we_n),
|
.ddr_we_n(ddr_we_n),
|
.ddr_cke(ddr_cke),
|
.ddr_cke(ddr_cke),
|
.ddr_cs_n(ddr_cs_n),
|
.ddr_cs_n(ddr_cs_n),
|
.ddr_a(ddr_a),
|
.ddr_a(ddr_a),
|
.ddr_ba(ddr_ba),
|
.ddr_ba(ddr_ba),
|
.ddr_dq(ddr_dq),
|
.ddr_dq(ddr_dq),
|
.ddr_dqs(ddr_dqs),
|
.ddr_dqs(ddr_dqs),
|
.ddr_dm(ddr_dm),
|
.ddr_dm(ddr_dm),
|
|
|
// Wishbone master interface
|
// Wishbone master interface
|
.wb_cyc_i(wb_cyc_ddr),
|
.wb_cyc_i(wb_cyc_ddr),
|
.wb_stb_i(wb_stb_ddr),
|
.wb_stb_i(wb_stb_ddr),
|
.wb_we_i(wb_we_ddr),
|
.wb_we_i(wb_we_ddr),
|
.wb_adr_i(wb_adr_ddr),
|
.wb_adr_i(wb_adr_ddr),
|
.wb_dat_o(wb_rdat_ddr),
|
.wb_dat_o(wb_rdat_ddr),
|
.wb_dat_i(wb_wdat_ddr),
|
.wb_dat_i(wb_wdat_ddr),
|
.wb_sel_i(wb_sel_ddr),
|
.wb_sel_i(wb_sel_ddr),
|
.wb_ack_o(wb_ack_ddr),
|
.wb_ack_o(wb_ack_ddr),
|
|
|
// phase shifting
|
// phase shifting
|
.rot(rot)
|
.rot(rot)
|
|
|
);
|
);
|
|
|
|
|
endmodule
|
endmodule
|
|
|
|
|