// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// This file is part of the M32632 project
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// This file is part of the M32632 project
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// http://opencores.org/project,m32632
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// http://opencores.org/project,m32632
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//
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//
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// Filename: M32632.v
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// Filename: M32632.v
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// Version: 3.0 Cache Interface reworked
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// Project: M32632
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// History: 2.1 bug fix of 26 November 2016
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// Version: 3.1 bug fix of 25 February 2019
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// History: 3.0 Cache Interface reworked
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// 2.1 bug fix of 26 November 2016
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// 2.0 50 MHz release of 14 August 2016
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// 2.0 50 MHz release of 14 August 2016
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// 1.1 bug fix of 7 October 2015
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// 1.1 bug fix of 7 October 2015
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// 1.0 first release of 30 Mai 2015
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// 1.0 first release of 30 Mai 2015
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// Date: 2 December 2018
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// Author: Udo Moeller
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// Date: 8 July 2017
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//
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//
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// Copyright (C) 2018 Udo Moeller
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// Copyright (C) 2019 Udo Moeller
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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// the original copyright notice and the associated disclaimer.
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//
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//
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// This source file is free software; you can redistribute it
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// This source file is free software; you can redistribute it
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// and/or modify it under the terms of the GNU Lesser General
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// and/or modify it under the terms of the GNU Lesser General
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// Public License as published by the Free Software Foundation;
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any
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// either version 2.1 of the License, or (at your option) any
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// later version.
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// later version.
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//
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//
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// This source is distributed in the hope that it will be
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// This source is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// PURPOSE. See the GNU Lesser General Public License for more
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// PURPOSE. See the GNU Lesser General Public License for more
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// details.
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// details.
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//
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//
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// You should have received a copy of the GNU Lesser General
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, download it
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// Public License along with this source; if not, download it
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// from http://www.opencores.org/lgpl.shtml
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// from http://www.opencores.org/lgpl.shtml
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//
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// Modules contained in this file:
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// Modules contained in this file:
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// M32632 The top level of M32632
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// M32632 The top level of M32632
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//
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module M32632( BCLK, DRAMSZ, BRESET, NMI_N, INT_N, STATUS, ILO, STATSIGS,
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module M32632( BCLK, DRAMSZ, BRESET, NMI_N, INT_N, STATUS, ILO, STATSIGS,
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IO_WR, IO_RD, IO_A, IO_BE, IO_DI, IO_Q, IO_READY,
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IO_WR, IO_RD, IO_A, IO_BE, IO_DI, IO_Q, IO_READY,
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ENDRAM, IC_MDONE, DC_MDONE, ENWR, DRAM_Q, DC_INHIBIT, IC_INHIBIT,
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ENDRAM, IC_MDONE, DC_MDONE, ENWR, DRAM_Q, DC_INHIBIT, IC_INHIBIT,
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IC_ACC, IDRAM_ADR, DC_ACC, DC_WR, DRAM_ADR, DRAM_DI,
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IC_ACC, IDRAM_ADR, DC_ACC, DC_WR, DRAM_ADR, DRAM_DI,
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HOLD, HLDA, DMA_CHK, DMA_AA,
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HOLD, HLDA, DMA_CHK, DMA_AA,
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COP_GO, COP_OP, COP_OUT, COP_DONE, COP_IN );
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COP_GO, COP_OP, COP_OUT, COP_DONE, COP_IN );
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// ++++++++++ Basic Signals
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// ++++++++++ Basic Signals
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input BCLK; // Basic Clock for everything
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input BCLK; // Basic Clock for everything
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input [2:0] DRAMSZ;
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input [2:0] DRAMSZ;
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input BRESET;
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input BRESET;
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input NMI_N;
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input NMI_N;
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input INT_N;
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input INT_N;
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output [3:0] STATUS;
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output [3:0] STATUS;
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output ILO;
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output ILO;
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output [7:0] STATSIGS;
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output [7:0] STATSIGS;
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// +++++++++ General Purpose Interface
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// +++++++++ General Purpose Interface
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output IO_WR;
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output IO_WR;
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output IO_RD;
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output IO_RD;
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output [31:0] IO_A;
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output [31:0] IO_A;
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output [3:0] IO_BE;
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output [3:0] IO_BE;
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output [31:0] IO_DI;
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output [31:0] IO_DI;
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input [31:0] IO_Q;
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input [31:0] IO_Q;
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input IO_READY;
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input IO_READY;
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// +++++++++ DRAM Interface In
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// +++++++++ DRAM Interface In
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input ENDRAM;
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input ENDRAM;
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input IC_MDONE;
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input IC_MDONE;
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input DC_MDONE;
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input DC_MDONE;
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input ENWR;
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input ENWR;
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input [127:0] DRAM_Q;
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input [127:0] DRAM_Q;
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input DC_INHIBIT;
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input DC_INHIBIT;
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input IC_INHIBIT;
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input IC_INHIBIT;
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// +++++++++ DRAM Interface Out
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// +++++++++ DRAM Interface Out
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output IC_ACC;
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output IC_ACC;
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output [28:0] IDRAM_ADR;
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output [28:0] IDRAM_ADR;
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output DC_ACC;
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output DC_ACC;
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output DC_WR;
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output DC_WR;
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output [28:0] DRAM_ADR;
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output [28:0] DRAM_ADR;
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output [35:0] DRAM_DI;
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output [35:0] DRAM_DI;
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// ++++++++++ DMA Interface
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// ++++++++++ DMA Interface
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input HOLD;
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input HOLD;
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output HLDA;
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output HLDA;
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input DMA_CHK;
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input DMA_CHK;
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input [28:4] DMA_AA;
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input [28:4] DMA_AA;
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// ++++++++++ Coprocessor Interface
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// ++++++++++ Coprocessor Interface
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output COP_GO;
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output COP_GO;
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output [23:0] COP_OP;
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output [23:0] COP_OP;
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output [127:0] COP_OUT;
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output [127:0] COP_OUT;
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input COP_DONE;
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input COP_DONE;
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input [63:0] COP_IN;
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input [63:0] COP_IN;
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wire ACC_DONE;
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wire ACC_DONE;
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wire [5:0] ACC_STAT;
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wire [5:0] ACC_STAT;
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wire [12:0] CFG;
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wire [12:0] CFG;
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wire [3:0] CINV;
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wire [3:0] CINV;
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wire DATA_HOLD;
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wire DATA_HOLD;
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wire DC_INIT;
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wire DC_INIT;
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wire Y_INIT;
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wire Y_INIT;
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wire DONE;
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wire DONE;
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wire [63:0] DP_Q;
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wire [63:0] DP_Q;
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wire [3:0] IACC_STAT;
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wire [3:0] IACC_STAT;
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wire PROT_ERROR;
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wire PROT_ERROR;
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wire [2:0] GENSTAT;
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wire [2:0] GENSTAT;
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wire IC_INIT;
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wire IC_INIT;
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wire IC_PREQ;
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wire IC_PREQ;
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wire IC_READ;
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wire IC_READ;
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wire [1:0] IC_SIGS;
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wire [1:0] IC_SIGS;
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wire IC_USER;
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wire IC_USER;
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wire [31:12] IC_VA;
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wire [31:12] IC_VA;
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wire [3:0] ICTODC;
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wire [3:0] ICTODC;
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wire [6:0] INFO_AU;
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wire [6:0] INFO_AU;
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wire [1:0] IVAR;
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wire [1:0] IVAR;
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wire IVAR_MUX;
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wire KDET;
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wire KDET;
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wire [28:4] KOLLI_A;
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wire [28:4] KOLLI_A;
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wire [3:0] MCR;
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wire [3:0] MCR;
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wire [23:0] MMU_DIN;
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wire [23:0] MMU_DIN;
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wire [11:0] PSR;
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wire [11:0] PSR;
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wire PTB_SEL;
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wire PTB_SEL;
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wire PTB_WR;
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wire PTB_WR;
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wire READ;
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wire READ;
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wire WRITE;
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wire WRITE;
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wire ZTEST;
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wire ZTEST;
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wire RMW;
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wire RMW;
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wire QWATWO;
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wire QWATWO;
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wire [2:0] RWVAL;
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wire [2:0] RWVAL;
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wire RWVFLAG;
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wire RWVFLAG;
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wire [3:0] D_IOBE;
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wire [3:0] D_IOBE;
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wire D_IORDY;
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wire D_IORDY;
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wire [1:0] CTRL_QW;
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wire [1:0] CTRL_QW;
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wire [3:0] PACKET;
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wire [3:0] PACKET;
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wire [1:0] SIZE;
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wire [1:0] SIZE;
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wire [31:0] VADR;
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wire [31:0] VADR;
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wire WREN_REG;
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wire WREN_REG;
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wire LD_DIN;
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wire LD_DIN;
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wire LD_IMME;
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wire LD_IMME;
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wire WR_REG;
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wire WR_REG;
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wire [14:0] ACC_FELD;
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wire [14:0] ACC_FELD;
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wire [31:0] DIN;
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wire [31:0] DIN;
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wire [31:0] DISP;
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wire [31:0] DISP;
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wire [2:0] IC_TEX;
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wire [2:0] IC_TEX;
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wire [31:0] IMME_Q;
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wire [31:0] IMME_Q;
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wire [1:0] LD_OUT;
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wire [1:0] LD_OUT;
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wire [12:0] DETOIP;
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wire [12:0] DETOIP;
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wire [1:0] MMU_UPDATE;
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wire [1:0] MMU_UPDATE;
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wire [10:0] OPER;
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wire [10:0] OPER;
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wire [31:0] PC_ARCHI;
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wire [31:0] PC_ARCHI;
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wire [31:0] PC_ICACHE;
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wire [31:0] PC_ICACHE;
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wire [7:0] RDAA;
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wire [7:0] RDAA;
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wire [7:0] RDAB;
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wire [7:0] RDAB;
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wire [1:0] START;
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wire [1:0] START;
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wire [1:0] WMASKE;
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wire [1:0] WMASKE;
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wire [5:0] WRADR;
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wire [5:0] WRADR;
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wire I_IORDY;
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wire I_IORDY;
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wire ACB_ZERO;
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wire ACB_ZERO;
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wire DC_ABORT;
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wire DC_ABORT;
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wire SAVE_PC;
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wire SAVE_PC;
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wire [31:0] IC_DIN;
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wire [31:0] IC_DIN;
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wire [31:0] PC_NEW;
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wire [31:0] PC_NEW;
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wire [4:0] STRING;
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wire [4:0] STRING;
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wire [5:0] TRAPS;
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wire [5:0] TRAPS;
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wire I_IORD;
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wire I_IORD;
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wire D_IOWR;
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wire D_IOWR;
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wire D_IORD;
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wire D_IORD;
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wire [31:0] D_IOA;
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wire [31:0] D_IOA;
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wire [31:0] I_IOA;
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wire [31:0] I_IOA;
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wire ENA_HK;
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wire ENA_HK;
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wire STOP_CINV;
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wire STOP_CINV;
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wire KOLLISION;
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wire KOLLISION;
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wire ILO_SIG;
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wire ILO_SIG;
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wire [1:0] PTE_STAT;
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wire [1:0] PTE_STAT;
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wire DBG_HIT;
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wire DBG_HIT;
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wire [40:2] DBG_IN;
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wire [40:2] DBG_IN;
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// The Data Cache
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// The Data Cache
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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DCACHE ARMS(
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DCACHE ARMS(
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.BCLK(BCLK),
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.BCLK(BCLK),
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.DRAMSZ(DRAMSZ),
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.DRAMSZ(DRAMSZ),
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.BRESET(BRESET),
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.BRESET(BRESET),
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.PTB_WR(PTB_WR),
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.PTB_WR(PTB_WR),
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.PTB_SEL(PTB_SEL),
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.PTB_SEL(PTB_SEL),
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.MDONE(DC_MDONE),
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.MDONE(DC_MDONE),
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.IO_READY(D_IORDY),
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.IO_READY(D_IORDY),
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.CTRL_QW(CTRL_QW),
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.CTRL_QW(CTRL_QW),
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.PSR_USER(INFO_AU[1]),
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.PSR_USER(INFO_AU[1]),
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.WRITE(WRITE),
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.WRITE(WRITE),
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.READ(READ),
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.READ(READ),
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.ZTEST(ZTEST),
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.ZTEST(ZTEST),
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.RMW(RMW),
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.RMW(RMW),
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.QWATWO(QWATWO),
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.QWATWO(QWATWO),
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.ENWR(ENWR),
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.ENWR(ENWR),
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.IC_PREQ(IC_PREQ),
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.IC_PREQ(IC_PREQ),
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.DMA_CHK(DMA_CHK),
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.DMA_CHK(DMA_CHK),
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.CFG(CFG[10:9]),
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.CFG(CFG[10:9]),
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.ENDRAM(ENDRAM),
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.ENDRAM(ENDRAM),
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.CINVAL(CINV[1:0]),
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.CINVAL(CINV[1:0]),
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.DMA_AA(DMA_AA),
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.DMA_AA(DMA_AA),
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.DP_Q(DP_Q),
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.DP_Q(DP_Q),
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.DRAM_Q(DRAM_Q),
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.DRAM_Q(DRAM_Q),
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.IC_VA(IC_VA),
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.IC_VA(IC_VA),
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.ICTODC(ICTODC),
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.ICTODC(ICTODC),
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.IO_Q(IO_Q),
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.IO_Q(IO_Q),
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.IVAR(IVAR),
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.IVAR(IVAR),
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.MCR_FLAGS(MCR),
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.MCR_FLAGS(MCR),
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.PACKET(PACKET),
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.PACKET(PACKET),
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.SIZE(SIZE),
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.SIZE(SIZE),
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.VADR(VADR),
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.VADR(VADR),
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.INHIBIT(DC_INHIBIT),
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.INHIBIT(DC_INHIBIT),
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.DRAM_ACC(DC_ACC),
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.DRAM_ACC(DC_ACC),
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.DRAM_WR(DC_WR),
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.DRAM_WR(DC_WR),
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.IO_RD(D_IORD),
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.IO_RD(D_IORD),
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.IO_WR(D_IOWR),
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.IO_WR(D_IOWR),
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.INIT_RUN(DC_INIT),
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.INIT_RUN(DC_INIT),
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.KDET(KDET),
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.KDET(KDET),
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.HLDA(HLDA),
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.HLDA(HLDA),
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.ACC_STAT(ACC_STAT),
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.ACC_STAT(ACC_STAT),
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.DP_DI(DIN),
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.DP_DI(DIN),
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.DRAM_A(DRAM_ADR),
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.DRAM_A(DRAM_ADR),
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.DRAM_DI(DRAM_DI),
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.DRAM_DI(DRAM_DI),
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.IACC_STAT(IACC_STAT[3:1]),
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.IACC_STAT(IACC_STAT[3:1]),
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.IC_SIGS(IC_SIGS),
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.IC_SIGS(IC_SIGS),
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.IO_A(D_IOA),
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.IO_A(D_IOA),
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.IO_BE(D_IOBE),
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.IO_BE(D_IOBE),
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.IO_DI(IO_DI),
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.IO_DI(IO_DI),
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.PTE_STAT(PTE_STAT),
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.PTE_STAT(PTE_STAT),
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.DBG_HIT(DBG_HIT),
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.DBG_HIT(DBG_HIT),
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.DBG_IN(DBG_IN),
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.DBG_IN(DBG_IN),
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.KOLLI_A(KOLLI_A),
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.KOLLI_A(KOLLI_A),
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.MMU_DIN(MMU_DIN),
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.MMU_DIN(MMU_DIN),
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.RWVAL(RWVAL),
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.RWVAL(RWVAL),
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.RWVFLAG(RWVFLAG));
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.RWVFLAG(RWVFLAG));
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|
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// The Datapath
|
// The Datapath
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
DATENPFAD STOMACH(
|
DATENPFAD STOMACH(
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.WREN(WREN_REG),
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.WREN(WREN_REG),
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.BRESET(BRESET),
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.BRESET(BRESET),
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.BCLK(BCLK),
|
.BCLK(BCLK),
|
.IO_READY(D_IORDY),
|
.IO_READY(D_IORDY),
|
.LD_DIN(LD_DIN),
|
.LD_DIN(LD_DIN),
|
.LD_IMME(LD_IMME),
|
.LD_IMME(LD_IMME),
|
.WR_REG(WR_REG),
|
.WR_REG(WR_REG),
|
.IC_USER(IC_USER),
|
.IC_USER(IC_USER),
|
.ACC_FELD(ACC_FELD),
|
.ACC_FELD(ACC_FELD),
|
.ACC_STAT(ACC_STAT),
|
.ACC_STAT(ACC_STAT),
|
.DIN(DIN),
|
.DIN(DIN),
|
.DISP(DISP),
|
.DISP(DISP),
|
.IC_TEX(IC_TEX),
|
.IC_TEX(IC_TEX),
|
.IMME_Q(IMME_Q),
|
.IMME_Q(IMME_Q),
|
.INFO_AU(INFO_AU),
|
.INFO_AU(INFO_AU),
|
.LD_OUT(LD_OUT),
|
.LD_OUT(LD_OUT),
|
.DETOIP(DETOIP),
|
.DETOIP(DETOIP),
|
.MMU_UPDATE(MMU_UPDATE),
|
.MMU_UPDATE(MMU_UPDATE),
|
.OPER(OPER),
|
.OPER(OPER),
|
.PC_ARCHI(PC_ARCHI),
|
.PC_ARCHI(PC_ARCHI),
|
.PC_ICACHE(PC_ICACHE),
|
.PC_ICACHE(PC_ICACHE),
|
.RDAA(RDAA),
|
.RDAA(RDAA),
|
.RDAB(RDAB),
|
.RDAB(RDAB),
|
.START(START),
|
.START(START),
|
.WMASKE(WMASKE),
|
.WMASKE(WMASKE),
|
.WRADR(WRADR),
|
.WRADR(WRADR),
|
.READ_OUT(READ),
|
.READ_OUT(READ),
|
.WRITE_OUT(WRITE),
|
.WRITE_OUT(WRITE),
|
.ZTEST(ZTEST),
|
.ZTEST(ZTEST),
|
.RMW(RMW),
|
.RMW(RMW),
|
.QWATWO(QWATWO),
|
.QWATWO(QWATWO),
|
.ACC_DONE(ACC_DONE),
|
.ACC_DONE(ACC_DONE),
|
.CTRL_QW(CTRL_QW),
|
.CTRL_QW(CTRL_QW),
|
.Y_INIT(Y_INIT),
|
.Y_INIT(Y_INIT),
|
.DONE(DONE),
|
.DONE(DONE),
|
.PTB_WR(PTB_WR),
|
.PTB_WR(PTB_WR),
|
.PTB_SEL(PTB_SEL),
|
.PTB_SEL(PTB_SEL),
|
.ACB_ZERO(ACB_ZERO),
|
.ACB_ZERO(ACB_ZERO),
|
.ABORT(DC_ABORT),
|
.ABORT(DC_ABORT),
|
.SAVE_PC(SAVE_PC),
|
.SAVE_PC(SAVE_PC),
|
.CFG(CFG),
|
.CFG(CFG),
|
.CINV(CINV),
|
.CINV(CINV),
|
.DP_Q(DP_Q),
|
.DP_Q(DP_Q),
|
.IVAR(IVAR),
|
.IVAR(IVAR),
|
|
.IVAR_MUX(IVAR_MUX),
|
.MCR(MCR),
|
.MCR(MCR),
|
.PACKET(PACKET),
|
.PACKET(PACKET),
|
.PC_NEW(PC_NEW),
|
.PC_NEW(PC_NEW),
|
.PSR(PSR),
|
.PSR(PSR),
|
.SIZE(SIZE),
|
.SIZE(SIZE),
|
.STRING(STRING),
|
.STRING(STRING),
|
.TRAPS(TRAPS),
|
.TRAPS(TRAPS),
|
.VADR(VADR),
|
.VADR(VADR),
|
.RWVFLAG(RWVFLAG),
|
.RWVFLAG(RWVFLAG),
|
.DBG_HIT(DBG_HIT),
|
.DBG_HIT(DBG_HIT),
|
.DBG_IN(DBG_IN),
|
.DBG_IN(DBG_IN),
|
.COP_DONE(COP_DONE),
|
.COP_DONE(COP_DONE),
|
.COP_OP(COP_OP),
|
.COP_OP(COP_OP),
|
.COP_IN(COP_IN),
|
.COP_IN(COP_IN),
|
.COP_GO(COP_GO),
|
.COP_GO(COP_GO),
|
.COP_OUT(COP_OUT));
|
.COP_OUT(COP_OUT));
|
|
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// The Instruction Cache
|
// The Instruction Cache
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
ICACHE LEGS(
|
ICACHE LEGS(
|
.BCLK(BCLK),
|
.BCLK(BCLK),
|
.DRAMSZ(DRAMSZ),
|
.DRAMSZ(DRAMSZ),
|
.BRESET(BRESET),
|
.BRESET(BRESET),
|
.PTB_WR(PTB_WR),
|
.PTB_WR(PTB_WR),
|
.PTB_SEL(PTB_SEL),
|
.PTB_SEL(PTB_SEL),
|
.MDONE(IC_MDONE),
|
.MDONE(IC_MDONE),
|
.IO_READY(I_IORDY),
|
.IO_READY(I_IORDY),
|
.READ_I(IC_READ),
|
.READ_I(IC_READ),
|
.PSR_USER(IC_USER),
|
.PSR_USER(IC_USER),
|
.DATA_HOLD(DATA_HOLD),
|
.DATA_HOLD(DATA_HOLD),
|
.DRAM_WR(DC_WR),
|
.DRAM_WR(DC_WR),
|
.KDET(KDET),
|
.KDET(KDET),
|
.HOLD(HOLD),
|
.HOLD(HOLD),
|
.CFG(CFG[12:11]),
|
.CFG(CFG[12:11]),
|
.ENDRAM(ENDRAM),
|
.ENDRAM(ENDRAM),
|
.DRAM_Q(DRAM_Q),
|
.DRAM_Q(DRAM_Q),
|
.CINVAL(CINV[3:2]),
|
.CINVAL(CINV[3:2]),
|
.IC_SIGS(IC_SIGS),
|
.IC_SIGS(IC_SIGS),
|
.IO_Q(IO_Q),
|
.IO_Q(IO_Q),
|
.IVAR(IVAR),
|
.IVAR(IVAR),
|
|
.IVAR_MUX(IVAR_MUX),
|
|
.VADR_D(VADR[31:12]),
|
.KOLLI_A(KOLLI_A),
|
.KOLLI_A(KOLLI_A),
|
.MCR_FLAGS(MCR),
|
.MCR_FLAGS(MCR),
|
.MMU_DIN(MMU_DIN),
|
.MMU_DIN(MMU_DIN),
|
.VADR(PC_ICACHE),
|
.VADR_I(PC_ICACHE),
|
.INHIBIT(IC_INHIBIT),
|
.INHIBIT(IC_INHIBIT),
|
.DRAM_ACC(IC_ACC),
|
.DRAM_ACC(IC_ACC),
|
.IO_RD(I_IORD),
|
.IO_RD(I_IORD),
|
.INIT_RUN(IC_INIT),
|
.INIT_RUN(IC_INIT),
|
.PROT_ERROR(PROT_ERROR),
|
.PROT_ERROR(PROT_ERROR),
|
.ACC_OK(IACC_STAT[0]),
|
.ACC_OK(IACC_STAT[0]),
|
.IC_PREQ(IC_PREQ),
|
.IC_PREQ(IC_PREQ),
|
.KOLLISION(KOLLISION),
|
.KOLLISION(KOLLISION),
|
.DRAM_A(IDRAM_ADR),
|
.DRAM_A(IDRAM_ADR),
|
.IC_DQ(IC_DIN),
|
.IC_DQ(IC_DIN),
|
.IC_VA(IC_VA),
|
.IC_VA(IC_VA),
|
.ICTODC(ICTODC),
|
.ICTODC(ICTODC),
|
.ENA_HK(ENA_HK),
|
.ENA_HK(ENA_HK),
|
.STOP_CINV(STOP_CINV),
|
.STOP_CINV(STOP_CINV),
|
.IO_A(I_IOA));
|
.IO_A(I_IOA));
|
|
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// The Control Unit
|
// The Control Unit
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
STEUERUNG BRAIN(
|
STEUERUNG BRAIN(
|
.BCLK(BCLK),
|
.BCLK(BCLK),
|
.BRESET(BRESET),
|
.BRESET(BRESET),
|
.DC_ACC_DONE(ACC_DONE),
|
.DC_ACC_DONE(ACC_DONE),
|
.ACB_ZERO(ACB_ZERO),
|
.ACB_ZERO(ACB_ZERO),
|
.DONE(DONE),
|
.DONE(DONE),
|
.NMI_N(NMI_N),
|
.NMI_N(NMI_N),
|
.INT_N(INT_N),
|
.INT_N(INT_N),
|
.DC_ABORT(DC_ABORT),
|
.DC_ABORT(DC_ABORT),
|
.IC_INIT(IC_INIT),
|
.IC_INIT(IC_INIT),
|
.DC_INIT(DC_INIT),
|
.DC_INIT(DC_INIT),
|
.Y_INIT(Y_INIT),
|
.Y_INIT(Y_INIT),
|
.SAVE_PC(SAVE_PC),
|
.SAVE_PC(SAVE_PC),
|
.CFG(CFG[8:0]),
|
.CFG(CFG[8:0]),
|
.IACC_STAT(IACC_STAT),
|
.IACC_STAT(IACC_STAT),
|
.PROT_ERROR(PROT_ERROR),
|
.PROT_ERROR(PROT_ERROR),
|
.IC_DIN(IC_DIN),
|
.IC_DIN(IC_DIN),
|
.PC_NEW(PC_NEW),
|
.PC_NEW(PC_NEW),
|
.PSR(PSR),
|
.PSR(PSR),
|
.STRING(STRING),
|
.STRING(STRING),
|
.TRAPS(TRAPS),
|
.TRAPS(TRAPS),
|
.IC_READ(IC_READ),
|
.IC_READ(IC_READ),
|
.DATA_HOLD(DATA_HOLD),
|
.DATA_HOLD(DATA_HOLD),
|
.LD_DIN(LD_DIN),
|
.LD_DIN(LD_DIN),
|
.LD_IMME(LD_IMME),
|
.LD_IMME(LD_IMME),
|
.WREN(WREN_REG),
|
.WREN(WREN_REG),
|
.WR_REG(WR_REG),
|
.WR_REG(WR_REG),
|
.GENSTAT(GENSTAT),
|
.GENSTAT(GENSTAT),
|
.IC_USER(IC_USER),
|
.IC_USER(IC_USER),
|
.ACC_FELD(ACC_FELD),
|
.ACC_FELD(ACC_FELD),
|
.DISP(DISP),
|
.DISP(DISP),
|
.IC_TEX(IC_TEX),
|
.IC_TEX(IC_TEX),
|
.IMME_Q(IMME_Q),
|
.IMME_Q(IMME_Q),
|
.INFO_AU(INFO_AU),
|
.INFO_AU(INFO_AU),
|
.LD_OUT(LD_OUT),
|
.LD_OUT(LD_OUT),
|
.DETOIP(DETOIP),
|
.DETOIP(DETOIP),
|
.MMU_UPDATE(MMU_UPDATE),
|
.MMU_UPDATE(MMU_UPDATE),
|
.OPER(OPER),
|
.OPER(OPER),
|
.PC_ARCHI(PC_ARCHI),
|
.PC_ARCHI(PC_ARCHI),
|
.PC_ICACHE(PC_ICACHE),
|
.PC_ICACHE(PC_ICACHE),
|
.RDAA(RDAA),
|
.RDAA(RDAA),
|
.RDAB(RDAB),
|
.RDAB(RDAB),
|
.START(START),
|
.START(START),
|
.WMASKE(WMASKE),
|
.WMASKE(WMASKE),
|
.WRADR(WRADR),
|
.WRADR(WRADR),
|
.ENA_HK(ENA_HK),
|
.ENA_HK(ENA_HK),
|
.STOP_CINV(STOP_CINV),
|
.STOP_CINV(STOP_CINV),
|
.COP_OP(COP_OP),
|
.COP_OP(COP_OP),
|
.ILO(ILO_SIG),
|
.ILO(ILO_SIG),
|
.RWVAL(RWVAL));
|
.RWVAL(RWVAL));
|
|
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// The Input/Output Interface
|
// The Input/Output Interface
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
IO_SWITCH ISWITCH(
|
IO_SWITCH ISWITCH(
|
.I_IORD(I_IORD),
|
.I_IORD(I_IORD),
|
.D_IOWR(D_IOWR),
|
.D_IOWR(D_IOWR),
|
.IO_READY(IO_READY),
|
.IO_READY(IO_READY),
|
.D_IORD(D_IORD),
|
.D_IORD(D_IORD),
|
.D_IOBE(D_IOBE),
|
.D_IOBE(D_IOBE),
|
.BRESET(BRESET),
|
.BRESET(BRESET),
|
.BCLK(BCLK),
|
.BCLK(BCLK),
|
.GENSTAT(GENSTAT),
|
.GENSTAT(GENSTAT),
|
.D_IOA(D_IOA),
|
.D_IOA(D_IOA),
|
.I_IOA(I_IOA),
|
.I_IOA(I_IOA),
|
.D_IORDY(D_IORDY),
|
.D_IORDY(D_IORDY),
|
.I_IORDY(I_IORDY),
|
.I_IORDY(I_IORDY),
|
.IO_RD(IO_RD),
|
.IO_RD(IO_RD),
|
.IO_WR(IO_WR),
|
.IO_WR(IO_WR),
|
.IO_BE(IO_BE),
|
.IO_BE(IO_BE),
|
.ILO_SIG(ILO_SIG),
|
.ILO_SIG(ILO_SIG),
|
.ILO(ILO),
|
.ILO(ILO),
|
.IO_A(IO_A),
|
.IO_A(IO_A),
|
.DCWACC({DC_WR,DC_ACC}),
|
.DCWACC({DC_WR,DC_ACC}),
|
.STATUS(STATUS));
|
.STATUS(STATUS));
|
|
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// The Statistic Signal Generator
|
// The Statistic Signal Generator
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
MAKE_STAT MKSTAT(
|
MAKE_STAT MKSTAT(
|
.BCLK(BCLK),
|
.BCLK(BCLK),
|
.READ(READ),
|
.READ(READ),
|
.DACC_OK(ACC_STAT[0]),
|
.DACC_OK(ACC_STAT[0]),
|
.KOLLISION(KOLLISION),
|
.KOLLISION(KOLLISION),
|
.DC_ACC(DC_ACC),
|
.DC_ACC(DC_ACC),
|
.DPTE_ACC(PTE_STAT[0]),
|
.DPTE_ACC(PTE_STAT[0]),
|
.DC_MDONE(DC_MDONE),
|
.DC_MDONE(DC_MDONE),
|
.DRAM_WR(DC_WR),
|
.DRAM_WR(DC_WR),
|
.IC_READ(IC_READ),
|
.IC_READ(IC_READ),
|
.IACC_OK(IACC_STAT[0]),
|
.IACC_OK(IACC_STAT[0]),
|
.IC_ACC(IC_ACC),
|
.IC_ACC(IC_ACC),
|
.IPTE_ACC(PTE_STAT[1]),
|
.IPTE_ACC(PTE_STAT[1]),
|
.IC_MDONE(IC_MDONE),
|
.IC_MDONE(IC_MDONE),
|
.DATA_HOLD(DATA_HOLD),
|
.DATA_HOLD(DATA_HOLD),
|
.STATSIGS(STATSIGS));
|
.STATSIGS(STATSIGS));
|
|
|
endmodule
|
endmodule
|
|
|
