// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// This file is part of the M32632 project
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// This file is part of the M32632 project
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// http://opencores.org/project,m32632
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// http://opencores.org/project,m32632
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//
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//
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// Filename: REGISTERS.v
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// Filename: REGISTERS.v
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// Version: 3.0
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// Project: M32632
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// Version: 3.1 bug fix of 25 February 2019
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// History: 1.0 first release of 30 Mai 2015
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// History: 1.0 first release of 30 Mai 2015
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// Date: 2 December 2018
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// Author: Udo Moeller
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// Date: 8 July 2017
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//
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//
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// Copyright (C) 2018 Udo Moeller
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// Copyright (C) 2019 Udo Moeller
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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// the original copyright notice and the associated disclaimer.
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//
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//
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// This source file is free software; you can redistribute it
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// This source file is free software; you can redistribute it
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// and/or modify it under the terms of the GNU Lesser General
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// and/or modify it under the terms of the GNU Lesser General
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// Public License as published by the Free Software Foundation;
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any
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// either version 2.1 of the License, or (at your option) any
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// later version.
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// later version.
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//
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//
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// This source is distributed in the hope that it will be
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// This source is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// PURPOSE. See the GNU Lesser General Public License for more
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// PURPOSE. See the GNU Lesser General Public License for more
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// details.
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// details.
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//
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//
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// You should have received a copy of the GNU Lesser General
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, download it
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// Public License along with this source; if not, download it
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// from http://www.opencores.org/lgpl.shtml
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// from http://www.opencores.org/lgpl.shtml
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//
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// Modules contained in this file:
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// Modules contained in this file:
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// 1. CONFIG_REGS Configuration and Debug Registers
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// 1. CONFIG_REGS Configuration and Debug Registers
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// 2. FP_STAT_REG Floating Point Status Register
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// 2. FP_STAT_REG Floating Point Status Register
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// 3. REGISTER General Purpose Registers
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// 3. REGISTER General Purpose Registers
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//
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// 1. CONFIG_REGS Configuration and Debug Registers
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// 1. CONFIG_REGS Configuration and Debug Registers
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//
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module CONFIG_REGS ( BCLK, BRESET, WREN, LD_OUT, OPCODE, SRC1, WRADR, PC_ARCHI, USER, PCMATCH, DBG_HIT, READ,
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module CONFIG_REGS ( BCLK, BRESET, WREN, LD_OUT, OPCODE, SRC1, WRADR, PC_ARCHI, USER, PCMATCH, DBG_HIT, READ,
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CFG, MCR, PTB_WR, PTB_SEL, IVAR, CINV, Y_INIT, DSR, DBG_TRAPS, DBG_IN );
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CFG, MCR, PTB_WR, PTB_SEL, IVAR, IVAR_MUX, CINV, Y_INIT, DSR, DBG_TRAPS, DBG_IN );
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input BCLK,BRESET;
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input BCLK,BRESET;
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input WREN,LD_OUT;
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input WREN,LD_OUT;
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input [7:0] OPCODE;
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input [7:0] OPCODE;
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input [31:0] SRC1;
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input [31:0] SRC1;
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input [5:0] WRADR;
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input [5:0] WRADR;
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input [31:0] PC_ARCHI;
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input [31:0] PC_ARCHI;
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input USER;
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input USER;
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input PCMATCH;
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input PCMATCH;
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input DBG_HIT;
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input DBG_HIT;
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input READ;
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input READ;
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output [12:0] CFG;
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output [12:0] CFG;
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output [3:0] MCR;
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output [3:0] MCR;
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output PTB_WR;
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output PTB_WR;
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output PTB_SEL;
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output PTB_SEL;
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output [1:0] IVAR;
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output [1:0] IVAR;
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output IVAR_MUX;
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output [3:0] CINV;
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output [3:0] CINV;
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output Y_INIT;
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output Y_INIT;
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output [3:0] DSR;
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output [3:0] DSR;
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output [2:0] DBG_TRAPS;
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output [2:0] DBG_TRAPS;
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output [40:2] DBG_IN;
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output [40:2] DBG_IN;
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reg [3:0] MCR;
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reg [3:0] MCR;
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reg [12:0] CFG;
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reg [12:0] CFG;
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reg [1:0] old_cfg;
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reg [1:0] old_cfg;
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reg PTB_WR,PTB_SEL;
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reg PTB_WR,PTB_SEL;
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reg ivarreg;
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reg ivarreg;
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reg [1:0] ci_all,ci_line;
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reg [1:0] ci_all,ci_line;
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reg check_y;
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reg check_y;
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wire ld_cfg,ld_mcr,do_cinv;
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wire ld_cfg,ld_mcr,do_cinv;
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wire init_ic,init_dc;
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wire init_ic,init_dc;
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wire op_ok;
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wire op_ok;
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assign op_ok = (OPCODE == 8'h6A); // Special Opcode - for security reason
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assign op_ok = (OPCODE == 8'h6A); // Special Opcode - for security reason
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assign ld_cfg = op_ok & (WRADR == 6'h1C) & WREN;
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assign ld_cfg = op_ok & (WRADR == 6'h1C) & WREN;
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assign ld_mcr = op_ok & (WRADR == 6'd9) & WREN;
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assign ld_mcr = op_ok & (WRADR == 6'd9) & WREN;
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assign do_cinv = op_ok & (WRADR[5:4] == 2'b11) & WREN;
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assign do_cinv = op_ok & (WRADR[5:4] == 2'b11) & WREN;
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// PF is not implemented
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// PF is not implemented
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always @(posedge BCLK or negedge BRESET)
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always @(posedge BCLK or negedge BRESET)
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if (!BRESET) CFG <= 13'h0;
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if (!BRESET) CFG <= 13'h0;
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else if (ld_cfg) CFG <= SRC1[12:0];
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else if (ld_cfg) CFG <= SRC1[12:0];
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always @(posedge BCLK or negedge BRESET)
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always @(posedge BCLK or negedge BRESET)
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if (!BRESET) MCR <= 4'h0;
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if (!BRESET) MCR <= 4'h0;
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else if (ld_mcr) MCR <= SRC1[3:0];
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else if (ld_mcr) MCR <= SRC1[3:0];
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always @(posedge BCLK) ivarreg <= op_ok & (WRADR[5:1] == 5'd7) & WREN; // IVAR0/1 = Reg. Nr. 14/15
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assign IVAR_MUX = op_ok & (WRADR[5:1] == 5'd7) & WREN; // IVAR0/1 = Reg. Nr. 14/15
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always @(posedge BCLK) ivarreg <= IVAR_MUX;
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assign IVAR = {ivarreg,PTB_SEL};
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assign IVAR = {ivarreg,PTB_SEL};
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always @(posedge BCLK) PTB_WR <= op_ok & (WRADR[5:1] == 5'd6) & WREN; // PTB0/1 = Reg. Nr. 12/13
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always @(posedge BCLK) PTB_WR <= op_ok & (WRADR[5:1] == 5'd6) & WREN; // PTB0/1 = Reg. Nr. 12/13
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always @(posedge BCLK) PTB_SEL <= WRADR[0];
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always @(posedge BCLK) PTB_SEL <= WRADR[0];
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// The Cache content will be invalid if the Enable-Bit is set to 0
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// The Cache content will be invalid if the Enable-Bit is set to 0
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always @(posedge BCLK) old_cfg <= {CFG[11],CFG[9]};
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always @(posedge BCLK) old_cfg <= {CFG[11],CFG[9]};
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// Cache Invalidate : the Flags are coming out of the Short-field which is otherwise used for Register selection
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// Cache Invalidate : the Flags are coming out of the Short-field which is otherwise used for Register selection
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always @(posedge BCLK) ci_all <= do_cinv & WRADR[2] ? WRADR[1:0] : 2'b0; // clear all
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always @(posedge BCLK) ci_all <= do_cinv & WRADR[2] ? WRADR[1:0] : 2'b0; // clear all
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always @(posedge BCLK) ci_line <= do_cinv & ~WRADR[2] ? WRADR[1:0] : 2'b0; // clear cache line
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always @(posedge BCLK) ci_line <= do_cinv & ~WRADR[2] ? WRADR[1:0] : 2'b0; // clear cache line
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assign init_ic = old_cfg[1] & (~CFG[11] | ci_all[1]);
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assign init_ic = old_cfg[1] & (~CFG[11] | ci_all[1]);
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assign init_dc = old_cfg[0] & (~CFG[9] | ci_all[0]);
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assign init_dc = old_cfg[0] & (~CFG[9] | ci_all[0]);
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assign CINV = {init_ic,ci_line[1],init_dc,ci_line[0]};
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assign CINV = {init_ic,ci_line[1],init_dc,ci_line[0]};
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// Y_INIT is neccessary if nothing has changed and therefore no DC/IC_INIT is generated
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// Y_INIT is neccessary if nothing has changed and therefore no DC/IC_INIT is generated
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always @(posedge BCLK) check_y <= ld_cfg | do_cinv;
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always @(posedge BCLK) check_y <= ld_cfg | do_cinv;
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assign Y_INIT = check_y & ~init_ic & ~init_dc; // goes to register "old_init"
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assign Y_INIT = check_y & ~init_ic & ~init_dc; // goes to register "old_init"
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// +++++++++++++ DEBUG Unit +++++++++++++++
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// +++++++++++++ DEBUG Unit +++++++++++++++
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reg [3:0] DSR;
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reg [3:0] DSR;
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reg [12:0] dcr;
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reg [12:0] dcr;
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reg [31:0] bpc;
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reg [31:0] bpc;
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reg [31:2] car;
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reg [31:2] car;
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wire op_dbg,ld_dcr,ld_bpc,ld_dsr,ld_car;
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wire op_dbg,ld_dcr,ld_bpc,ld_dsr,ld_car;
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wire enable;
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wire enable;
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assign op_dbg = (OPCODE == 8'h76);
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assign op_dbg = (OPCODE == 8'h76);
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assign ld_dcr = op_dbg & (WRADR == 6'h11) & WREN;
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assign ld_dcr = op_dbg & (WRADR == 6'h11) & WREN;
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assign ld_bpc = op_dbg & (WRADR == 6'h12) & WREN;
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assign ld_bpc = op_dbg & (WRADR == 6'h12) & WREN;
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assign ld_dsr = op_dbg & (WRADR == 6'h13) & WREN;
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assign ld_dsr = op_dbg & (WRADR == 6'h13) & WREN;
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assign ld_car = op_dbg & (WRADR == 6'h14) & WREN;
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assign ld_car = op_dbg & (WRADR == 6'h14) & WREN;
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assign enable = dcr[12] & (USER ? dcr[10] : dcr[11]); // DEN & (USER ? UD : SD)
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assign enable = dcr[12] & (USER ? dcr[10] : dcr[11]); // DEN & (USER ? UD : SD)
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always @(posedge BCLK or negedge BRESET)
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always @(posedge BCLK or negedge BRESET)
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if (!BRESET) dcr <= 13'd0;
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if (!BRESET) dcr <= 13'd0;
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else if (ld_dcr) dcr <= {SRC1[23:19],SRC1[7:0]};
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else if (ld_dcr) dcr <= {SRC1[23:19],SRC1[7:0]};
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always @(posedge BCLK) if (ld_bpc) bpc <= SRC1;
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always @(posedge BCLK) if (ld_bpc) bpc <= SRC1;
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always @(posedge BCLK) if (ld_car) car <= SRC1[31:2];
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always @(posedge BCLK) if (ld_car) car <= SRC1[31:2];
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// DEN SD DEN UD CAE CRD CAE CWR VNP/CBE CAR
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// DEN SD DEN UD CAE CRD CAE CWR VNP/CBE CAR
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assign DBG_IN = {(dcr[12] & dcr[11]),(dcr[12] & dcr[10]),(dcr[7] & dcr[6]),(dcr[7] & dcr[5]),dcr[4:0],car};
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assign DBG_IN = {(dcr[12] & dcr[11]),(dcr[12] & dcr[10]),(dcr[7] & dcr[6]),(dcr[7] & dcr[5]),dcr[4:0],car};
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always @(posedge BCLK or negedge BRESET)
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always @(posedge BCLK or negedge BRESET)
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if (!BRESET) DSR <= 4'd0;
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if (!BRESET) DSR <= 4'd0;
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else
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else
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if (ld_dsr) DSR <= SRC1[31:28];
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if (ld_dsr) DSR <= SRC1[31:28];
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else
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else
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begin
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begin
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DSR[3] <= DBG_HIT ? READ : DSR[3];
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DSR[3] <= DBG_HIT ? READ : DSR[3];
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DSR[2] <= DSR[2] | PCMATCH;
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DSR[2] <= DSR[2] | PCMATCH;
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DSR[1] <= DSR[1];
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DSR[1] <= DSR[1];
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DSR[0] <= DSR[0] | DBG_HIT;
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DSR[0] <= DSR[0] | DBG_HIT;
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end
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end
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assign DBG_TRAPS[0] = enable & dcr[9] & (PC_ARCHI == bpc); // dcr[9]=PCE
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assign DBG_TRAPS[0] = enable & dcr[9] & (PC_ARCHI == bpc); // dcr[9]=PCE
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assign DBG_TRAPS[1] = DBG_HIT; // Compare Adress Hit
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assign DBG_TRAPS[1] = DBG_HIT; // Compare Adress Hit
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assign DBG_TRAPS[2] = dcr[8]; // TR, Trap enable
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assign DBG_TRAPS[2] = dcr[8]; // TR, Trap enable
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endmodule
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endmodule
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// 2. FP_STAT_REG Floating Point Status Register
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// 2. FP_STAT_REG Floating Point Status Register
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//
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module FP_STAT_REG ( BCLK, BRESET, LFSR, UP_SP, UP_DP, TT_SP, TT_DP, WREN, WRADR, DIN, FSR, TWREN, FPU_TRAP, SAVE_PC);
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module FP_STAT_REG ( BCLK, BRESET, LFSR, UP_SP, UP_DP, TT_SP, TT_DP, WREN, WRADR, DIN, FSR, TWREN, FPU_TRAP, SAVE_PC);
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input BCLK;
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input BCLK;
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input BRESET;
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input BRESET;
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input LFSR; // Load by LFSR opcode
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input LFSR; // Load by LFSR opcode
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input UP_SP,UP_DP; // update if calculation operation
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input UP_SP,UP_DP; // update if calculation operation
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input [4:0] TT_SP,TT_DP;
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input [4:0] TT_SP,TT_DP;
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input WREN; // for RMB and LFSR
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input WREN; // for RMB and LFSR
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input [5:4] WRADR;
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input [5:4] WRADR;
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input [16:0] DIN; // Data for LFSR opcode
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input [16:0] DIN; // Data for LFSR opcode
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output [31:0] FSR;
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output [31:0] FSR;
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output TWREN;
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output TWREN;
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output reg FPU_TRAP;
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output reg FPU_TRAP;
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output SAVE_PC;
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output SAVE_PC;
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reg [4:3] trap_d;
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reg [4:3] trap_d;
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reg update_d;
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reg update_d;
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reg set_rm_d;
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reg set_rm_d;
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reg [10:0] set_bits;
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reg [10:0] set_bits;
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reg [4:0] flags;
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reg [4:0] flags;
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reg rm_bit;
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reg rm_bit;
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wire load_fsr;
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wire load_fsr;
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wire update,update_i;
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wire update,update_i;
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wire [4:0] trap;
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wire [4:0] trap;
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wire uflag,iflag,rmflag;
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wire uflag,iflag,rmflag;
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assign load_fsr = LFSR & WREN;
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assign load_fsr = LFSR & WREN;
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assign trap = UP_SP ? TT_SP : TT_DP;
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assign trap = UP_SP ? TT_SP : TT_DP;
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// This signal suppresses write into registers if FPU Trap, timing critical signal !
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// This signal suppresses write into registers if FPU Trap, timing critical signal !
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assign TWREN = ~((UP_SP & (TT_SP[2:0] != 3'b0)) | (UP_DP & (TT_DP[2:0] != 3'b0)));
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assign TWREN = ~((UP_SP & (TT_SP[2:0] != 3'b0)) | (UP_DP & (TT_DP[2:0] != 3'b0)));
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always @(posedge BCLK or negedge BRESET)
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always @(posedge BCLK or negedge BRESET)
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if (!BRESET) FPU_TRAP <= 1'b0;
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if (!BRESET) FPU_TRAP <= 1'b0;
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else FPU_TRAP <= ~FPU_TRAP & ~TWREN; // one pulse of one cycle informs the Opcode Decoder
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else FPU_TRAP <= ~FPU_TRAP & ~TWREN; // one pulse of one cycle informs the Opcode Decoder
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assign update_i = (UP_SP | UP_DP) & ~FPU_TRAP; // unfortunately one FPU opcode may follow !
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assign update_i = (UP_SP | UP_DP) & ~FPU_TRAP; // unfortunately one FPU opcode may follow !
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always @(posedge BCLK) update_d <= update_i;
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always @(posedge BCLK) update_d <= update_i;
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always @(posedge BCLK) trap_d <= trap[4:3];
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always @(posedge BCLK) trap_d <= trap[4:3];
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always @(posedge BCLK) set_rm_d <= WREN & (WRADR == 2'b10);
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always @(posedge BCLK) set_rm_d <= WREN & (WRADR == 2'b10);
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assign update = update_d & ~FPU_TRAP;
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assign update = update_d & ~FPU_TRAP;
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// The Flags are set and stay "1"
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// The Flags are set and stay "1"
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assign iflag = (update & trap_d[4]) | flags[4]; // Inexact Result
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assign iflag = (update & trap_d[4]) | flags[4]; // Inexact Result
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assign uflag = (update & trap_d[3]) | flags[3]; // Underflow
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assign uflag = (update & trap_d[3]) | flags[3]; // Underflow
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assign rmflag = (set_rm_d & ~FPU_TRAP) | rm_bit; // Register Modify
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assign rmflag = (set_rm_d & ~FPU_TRAP) | rm_bit; // Register Modify
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always @(posedge BCLK or negedge BRESET)
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always @(posedge BCLK or negedge BRESET)
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if (!BRESET) flags[4:3] <= 2'b0; // Inexact = Bit6, Underflow = Bit4
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if (!BRESET) flags[4:3] <= 2'b0; // Inexact = Bit6, Underflow = Bit4
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else
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else
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begin
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begin
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if (load_fsr) flags[4:3] <= {DIN[6],DIN[4]};
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if (load_fsr) flags[4:3] <= {DIN[6],DIN[4]};
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else
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else
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if (update) flags[4:3] <= {iflag,uflag};
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if (update) flags[4:3] <= {iflag,uflag};
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end
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end
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always @(posedge BCLK or negedge BRESET)
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always @(posedge BCLK or negedge BRESET)
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if (!BRESET) flags[2:0] <= 3'b0; // TT Field = Bit2-0
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if (!BRESET) flags[2:0] <= 3'b0; // TT Field = Bit2-0
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else
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else
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begin
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begin
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if (load_fsr) flags[2:0] <= DIN[2:0];
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if (load_fsr) flags[2:0] <= DIN[2:0];
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else
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else
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if (update_i) flags[2:0] <= trap[2:0];
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if (update_i) flags[2:0] <= trap[2:0];
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end
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end
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always @(posedge BCLK or negedge BRESET)
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always @(posedge BCLK or negedge BRESET)
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if (!BRESET) rm_bit <= 1'b0; // Register Modify Bit
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if (!BRESET) rm_bit <= 1'b0; // Register Modify Bit
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else
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else
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begin
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begin
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if (load_fsr) rm_bit <= DIN[16];
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if (load_fsr) rm_bit <= DIN[16];
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else
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else
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if (set_rm_d & ~FPU_TRAP) rm_bit <= 1'b1; // in case of TRAP there is no writing to Register
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if (set_rm_d & ~FPU_TRAP) rm_bit <= 1'b1; // in case of TRAP there is no writing to Register
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end
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end
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always @(posedge BCLK or negedge BRESET)
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always @(posedge BCLK or negedge BRESET)
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if (!BRESET) set_bits <= 11'b0; // all other Bits
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if (!BRESET) set_bits <= 11'b0; // all other Bits
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else
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else
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if (load_fsr) set_bits <= {DIN[15:7],DIN[5],DIN[3]};
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if (load_fsr) set_bits <= {DIN[15:7],DIN[5],DIN[3]};
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assign FSR = {15'h0,rmflag,set_bits[10:2],iflag,set_bits[1],uflag,set_bits[0],flags[2:0]};
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assign FSR = {15'h0,rmflag,set_bits[10:2],iflag,set_bits[1],uflag,set_bits[0],flags[2:0]};
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assign SAVE_PC = (UP_SP | UP_DP) & ~FPU_TRAP; // Store the correct PC for FPU Trap
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assign SAVE_PC = (UP_SP | UP_DP) & ~FPU_TRAP; // Store the correct PC for FPU Trap
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endmodule
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endmodule
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// 3. REGISTER General Purpose Registers
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// 3. REGISTER General Purpose Registers
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//
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module REGISTER( BCLK, ENWR, DOWR, BYDIN, DIN, RADR, WADR, WMASKE, DOUT, SELI );
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module REGISTER( BCLK, ENWR, DOWR, BYDIN, DIN, RADR, WADR, WMASKE, DOUT, SELI );
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input BCLK;
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input BCLK;
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input DOWR,ENWR;
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input DOWR,ENWR;
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input [31:0] BYDIN,DIN;
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input [31:0] BYDIN,DIN;
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input [7:0] RADR;
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input [7:0] RADR;
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input [5:0] WADR;
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input [5:0] WADR;
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input [1:0] WMASKE;
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input [1:0] WMASKE;
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output [31:0] DOUT;
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output [31:0] DOUT;
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output reg SELI;
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output reg SELI;
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reg [2:0] mx;
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reg [2:0] mx;
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wire [2:0] be;
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wire [2:0] be;
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wire eq_rw;
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wire eq_rw;
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// +++++++++++++++++++ Memories ++++++++++++++++++++
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// +++++++++++++++++++ Memories ++++++++++++++++++++
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reg [15:0] REGFILE_C [0:63]; // Byte 3 and 2 , Verilog allows no "Byte Write" in wider memories !!!
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reg [15:0] REGFILE_C [0:63]; // Byte 3 and 2 , Verilog allows no "Byte Write" in wider memories !!!
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reg [7:0] REGFILE_B [0:63]; // Byte 1
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reg [7:0] REGFILE_B [0:63]; // Byte 1
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reg [7:0] REGFILE_A [0:63]; // Byte 0
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reg [7:0] REGFILE_A [0:63]; // Byte 0
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reg [31:0] RF;
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reg [31:0] RF;
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assign be = {WMASKE[1],(WMASKE[1] | WMASKE[0]),1'b1};
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assign be = {WMASKE[1],(WMASKE[1] | WMASKE[0]),1'b1};
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assign eq_rw = ENWR & (RADR[5:0] == WADR);
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assign eq_rw = ENWR & (RADR[5:0] == WADR);
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always @(posedge BCLK) if (RADR[7]) mx[2:0] <= be[2:0] & {{3{eq_rw}}};
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always @(posedge BCLK) if (RADR[7]) mx[2:0] <= be[2:0] & {{3{eq_rw}}};
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always @(posedge BCLK) if (RADR[7]) SELI <= RADR[6];
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always @(posedge BCLK) if (RADR[7]) SELI <= RADR[6];
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assign DOUT[31:16] = mx[2] ? BYDIN[31:16] : RF[31:16];
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assign DOUT[31:16] = mx[2] ? BYDIN[31:16] : RF[31:16];
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assign DOUT[15:8] = mx[1] ? BYDIN[15:8] : RF[15:8];
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assign DOUT[15:8] = mx[1] ? BYDIN[15:8] : RF[15:8];
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assign DOUT[7:0] = mx[0] ? BYDIN[7:0] : RF[7:0];
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assign DOUT[7:0] = mx[0] ? BYDIN[7:0] : RF[7:0];
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// ++++++++++++++++ Register File 64 * 32 Bits ++++++++++++
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// ++++++++++++++++ Register File 64 * 32 Bits ++++++++++++
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|
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always @(posedge BCLK)
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always @(posedge BCLK)
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if (RADR[7])
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if (RADR[7])
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begin
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begin
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RF[31:16] <= REGFILE_C[RADR[5:0]];
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RF[31:16] <= REGFILE_C[RADR[5:0]];
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RF[15:8] <= REGFILE_B[RADR[5:0]];
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RF[15:8] <= REGFILE_B[RADR[5:0]];
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RF[7:0] <= REGFILE_A[RADR[5:0]];
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RF[7:0] <= REGFILE_A[RADR[5:0]];
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end
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end
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|
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always @(posedge BCLK)
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always @(posedge BCLK)
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if (DOWR)
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if (DOWR)
|
begin
|
begin
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if (be[2]) REGFILE_C[WADR] <= DIN[31:16];
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if (be[2]) REGFILE_C[WADR] <= DIN[31:16];
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if (be[1]) REGFILE_B[WADR] <= DIN[15:8];
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if (be[1]) REGFILE_B[WADR] <= DIN[15:8];
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if (be[0]) REGFILE_A[WADR] <= DIN[7:0];
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if (be[0]) REGFILE_A[WADR] <= DIN[7:0];
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end
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end
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endmodule
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endmodule
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