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Subversion Repositories mblite

[/] [mblite/] [trunk/] [designs/] [core_decoder_wb/] [wb_stdio.vhd] - Diff between revs 2 and 6

Rev 2	Rev 6
Line 30...	Line 30...
`END wb_stdio;`	`END wb_stdio;`

`ARCHITECTURE arch OF wb_stdio IS`	`ARCHITECTURE arch OF wb_stdio IS`
`CONSTANT ack_assert_delay : TIME := 2 ns;`	`CONSTANT ack_assert_delay : TIME := 2 ns;`
`CONSTANT ack_deassert_delay : TIME := 2 ns;`	`CONSTANT ack_deassert_delay : TIME := 2 ns;`
`SIGNAL ack : std_ulogic;`	`SIGNAL ack : std_logic;`
`SIGNAL chr_dat : std_ulogic_vector(31 DOWNTO 0);`	`SIGNAL chr_dat : std_logic_vector(31 DOWNTO 0);`
`SIGNAL chr_cnt : natural := 0;`	`SIGNAL chr_cnt : natural := 0;`
`BEGIN`	`BEGIN`
`wb_o.int_o <= '0';`	`wb_o.int_o <= '0';`
`wb_o.dat_o <= chr_dat;`	`wb_o.dat_o <= chr_dat;`
`-- Character device`	`-- Character device`
`stdio: PROCESS(wb_i.clk_i)`	`stdio: PROCESS(wb_i.clk_i)`
`VARIABLE s : line;`	`VARIABLE s : line;`
`VARIABLE byte : std_ulogic_vector(7 DOWNTO 0);`	`VARIABLE byte : std_logic_vector(7 DOWNTO 0);`
`VARIABLE char : character;`	`VARIABLE char : character;`
`BEGIN`	`BEGIN`
`IF rising_edge(wb_i.clk_i) THEN`	`IF rising_edge(wb_i.clk_i) THEN`
`IF (wb_i.stb_i AND wb_i.cyc_i) = '1' THEN`	`IF (wb_i.stb_i AND wb_i.cyc_i) = '1' THEN`
`IF wb_i.we_i = '1' AND ack = '0' THEN`	`IF wb_i.we_i = '1' AND ack = '0' THEN`