| Line 40... |
Line 40... |
dbg_dmem_o_dat_o : out STD_LOGIC_VECTOR(31 downto 0);
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dbg_dmem_o_dat_o : out STD_LOGIC_VECTOR(31 downto 0);
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dbg_dmem_o_sel_o : out STD_LOGIC_VECTOR( 3 downto 0)
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dbg_dmem_o_sel_o : out STD_LOGIC_VECTOR( 3 downto 0)
|
);
|
);
|
END COMPONENT;
|
END COMPONENT;
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|
|
SIGNAL sys_clk_i : std_ulogic := '0';
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SIGNAL sys_clk_i : std_logic := '0';
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SIGNAL sys_int_i : std_ulogic := '0';
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SIGNAL sys_int_i : std_logic := '0';
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SIGNAL sys_rst_i : std_ulogic := '0';
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SIGNAL sys_rst_i : std_logic := '0';
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SIGNAL sys_ena_i : std_ulogic := '1';
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SIGNAL sys_ena_i : std_logic := '1';
|
|
|
SIGNAL dmem_o : dmem_out_type;
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SIGNAL dmem_o : dmem_out_type;
|
|
|
CONSTANT std_out_adr : std_ulogic_vector(CFG_DMEM_SIZE - 1 DOWNTO 0) := X"FFFFFFC0";
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CONSTANT std_out_adr : std_logic_vector(CFG_DMEM_SIZE - 1 DOWNTO 0) := X"FFFFFFC0";
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BEGIN
|
BEGIN
|
|
|
sys_clk_i <= NOT sys_clk_i AFTER 10000 ps;
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sys_clk_i <= NOT sys_clk_i AFTER 10000 ps;
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sys_rst_i <= '1' AFTER 0 ps, '0' AFTER 150000 ps;
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sys_rst_i <= '1' AFTER 0 ps, '0' AFTER 150000 ps;
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sys_int_i <= '1' AFTER 500000000 ps, '0' after 500040000 ps;
|
sys_int_i <= '1' AFTER 500000000 ps, '0' after 500040000 ps;
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| Line 77... |
Line 77... |
END PROCESS;
|
END PROCESS;
|
|
|
-- Character device
|
-- Character device
|
stdio: PROCESS(sys_clk_i)
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stdio: PROCESS(sys_clk_i)
|
VARIABLE s : line;
|
VARIABLE s : line;
|
VARIABLE byte : std_ulogic_vector(7 DOWNTO 0);
|
VARIABLE byte : std_logic_vector(7 DOWNTO 0);
|
VARIABLE char : character;
|
VARIABLE char : character;
|
BEGIN
|
BEGIN
|
|
|
IF rising_edge(sys_clk_i) THEN
|
IF rising_edge(sys_clk_i) THEN
|
IF (NOT sys_rst_i AND dmem_o.ena_o AND compare(dmem_o.adr_o, std_out_adr)) = '1' THEN
|
IF (NOT sys_rst_i AND dmem_o.ena_o AND compare(dmem_o.adr_o, std_out_adr)) = '1' THEN
|
