| Line 11... |
Line 11... |
-- is registered for multicycle transfers. This adapter implements
|
-- is registered for multicycle transfers. This adapter implements
|
-- the synchronous Wishbone Bus protocol, Rev3B.
|
-- the synchronous Wishbone Bus protocol, Rev3B.
|
--
|
--
|
----------------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------------
|
|
|
LIBRARY ieee;
|
library ieee;
|
USE ieee.std_logic_1164.ALL;
|
use ieee.std_logic_1164.all;
|
USE ieee.std_logic_unsigned.ALL;
|
use ieee.std_logic_unsigned.all;
|
|
|
LIBRARY mblite;
|
library mblite;
|
USE mblite.config_Pkg.ALL;
|
use mblite.config_Pkg.all;
|
USE mblite.core_Pkg.ALL;
|
use mblite.core_Pkg.all;
|
USE mblite.std_Pkg.ALL;
|
use mblite.std_Pkg.all;
|
|
|
ENTITY core_wb_adapter IS PORT
|
entity core_wb_adapter is port
|
(
|
(
|
dmem_i : OUT dmem_in_type;
|
dmem_i : out dmem_in_type;
|
wb_o : OUT wb_mst_out_type;
|
wb_o : out wb_mst_out_type;
|
dmem_o : IN dmem_out_type;
|
dmem_o : in dmem_out_type;
|
wb_i : IN wb_mst_in_type
|
wb_i : in wb_mst_in_type
|
);
|
);
|
END core_wb_adapter;
|
end core_wb_adapter;
|
|
|
ARCHITECTURE arch OF core_wb_adapter IS
|
architecture arch of core_wb_adapter is
|
|
|
SIGNAL r_cyc_o : std_logic;
|
signal r_cyc_o : std_logic;
|
SIGNAL rin_cyc_o : std_logic;
|
signal rin_cyc_o : std_logic;
|
SIGNAL r_data, rin_data : std_logic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
|
signal r_data, rin_data : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
|
SIGNAL s_wait : std_logic;
|
signal s_wait : std_logic;
|
|
|
BEGIN
|
begin
|
|
|
-- Direct input-output connections
|
-- Direct input-output connections
|
wb_o.adr_o <= dmem_o.adr_o;
|
wb_o.adr_o <= dmem_o.adr_o;
|
wb_o.sel_o <= dmem_o.sel_o;
|
wb_o.sel_o <= dmem_o.sel_o;
|
wb_o.we_o <= dmem_o.we_o;
|
wb_o.we_o <= dmem_o.we_o;
|
dmem_i.dat_i <= wb_i.dat_i;
|
dmem_i.dat_i <= wb_i.dat_i;
|
|
|
-- synchronous bus control connections
|
-- synchronous bus control connections
|
wb_o.cyc_o <= r_cyc_o OR wb_i.ack_i;
|
wb_o.cyc_o <= r_cyc_o or wb_i.ack_i;
|
wb_o.stb_o <= r_cyc_o;
|
wb_o.stb_o <= r_cyc_o;
|
|
|
-- asynchronous core enable connection
|
-- asynchronous core enable connection
|
dmem_i.ena_i <= '0' WHEN (dmem_o.ena_o = '1' AND rin_cyc_o = '1') OR s_wait = '1' ELSE '1';
|
dmem_i.ena_i <= '0' when (dmem_o.ena_o = '1' and rin_cyc_o = '1') or s_wait = '1' else '1';
|
wb_o.dat_o <= rin_data;
|
wb_o.dat_o <= rin_data;
|
|
|
-- logic for wishbone master
|
-- logic for wishbone master
|
wb_adapter_comb: PROCESS(wb_i, dmem_o, r_cyc_o, r_data)
|
wb_adapter_comb: process(wb_i, dmem_o, r_cyc_o, r_data)
|
BEGIN
|
begin
|
|
|
IF wb_i.rst_i = '1' THEN
|
if wb_i.rst_i = '1' then
|
-- reset bus
|
-- reset bus
|
rin_data <= r_data;
|
rin_data <= r_data;
|
rin_cyc_o <= '0';
|
rin_cyc_o <= '0';
|
s_wait <= '0';
|
s_wait <= '0';
|
ELSIF r_cyc_o = '1' AND wb_i.ack_i = '1' THEN
|
elsif r_cyc_o = '1' and wb_i.ack_i = '1' then
|
-- terminate wishbone cycle
|
-- terminate wishbone cycle
|
rin_data <= r_data;
|
rin_data <= r_data;
|
rin_cyc_o <= '0';
|
rin_cyc_o <= '0';
|
s_wait <= '0';
|
s_wait <= '0';
|
ELSIF dmem_o.ena_o = '1' AND wb_i.ack_i = '1' THEN
|
elsif dmem_o.ena_o = '1' and wb_i.ack_i = '1' then
|
-- wishbone bus is occuppied
|
-- wishbone bus is occuppied
|
rin_data <= r_data;
|
rin_data <= r_data;
|
rin_cyc_o <= '1';
|
rin_cyc_o <= '1';
|
s_wait <= '1';
|
s_wait <= '1';
|
ELSIF r_cyc_o = '0' AND dmem_o.ena_o = '1' AND wb_i.ack_i = '0' THEN
|
elsif r_cyc_o = '0' and dmem_o.ena_o = '1' and wb_i.ack_i = '0' then
|
-- start wishbone cycle
|
-- start wishbone cycle
|
rin_data <= dmem_o.dat_o;
|
rin_data <= dmem_o.dat_o;
|
rin_cyc_o <= '1';
|
rin_cyc_o <= '1';
|
s_wait <= '0';
|
s_wait <= '0';
|
ELSE
|
else
|
-- maintain wishbone cycle
|
-- maintain wishbone cycle
|
rin_data <= r_data;
|
rin_data <= r_data;
|
rin_cyc_o <= r_cyc_o;
|
rin_cyc_o <= r_cyc_o;
|
s_wait <= '0';
|
s_wait <= '0';
|
END IF;
|
end if;
|
|
|
END PROCESS;
|
end process;
|
|
|
wb_adapter_seq: PROCESS(wb_i.clk_i)
|
wb_adapter_seq: process(wb_i.clk_i)
|
BEGIN
|
begin
|
IF rising_edge(wb_i.clk_i) THEN
|
if rising_edge(wb_i.clk_i) then
|
r_cyc_o <= rin_cyc_o;
|
r_cyc_o <= rin_cyc_o;
|
r_data <= rin_data;
|
r_data <= rin_data;
|
END IF;
|
end if;
|
END PROCESS;
|
end process;
|
|
|
END arch;
|
end arch;
|
|
|
No newline at end of file
|
No newline at end of file
|
