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--
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--
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-- Input file : fetch.vhd
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-- Input file : fetch.vhd
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-- Design name : fetch
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-- Design name : fetch
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-- Author : Tamar Kranenburg
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-- Author : Tamar Kranenburg
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-- Company : Delft University of Technology
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-- Company : Delft University of Technology
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-- : Faculty EEMCS, Department ME&CE
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-- : Faculty EEMCS, Department ME&CE
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-- : Systems and Circuits group
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-- : Systems and Circuits group
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--
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--
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-- Description : Instruction Fetch Stage inserts instruction into the pipeline. It
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-- Description : Instruction Fetch Stage inserts instruction into the pipeline. It
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-- uses a single port Random Access Memory component which holds
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-- uses a single port Random Access Memory component which holds
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-- the instructions. The next instruction is computed in the decode
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-- the instructions. The next instruction is computed in the decode
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-- stage.
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-- stage.
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--
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--
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_unsigned.ALL;
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USE ieee.std_logic_unsigned.ALL;
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LIBRARY mblite;
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LIBRARY mblite;
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USE mblite.config_Pkg.ALL;
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USE mblite.config_Pkg.ALL;
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USE mblite.core_Pkg.ALL;
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USE mblite.core_Pkg.ALL;
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USE mblite.std_Pkg.ALL;
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USE mblite.std_Pkg.ALL;
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ENTITY fetch IS PORT
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ENTITY fetch IS PORT
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(
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(
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fetch_o : OUT fetch_out_type;
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fetch_o : OUT fetch_out_type;
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imem_o : OUT imem_out_type;
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imem_o : OUT imem_out_type;
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fetch_i : IN fetch_in_type;
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fetch_i : IN fetch_in_type;
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rst_i : IN std_ulogic;
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rst_i : IN std_logic;
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ena_i : IN std_ulogic;
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ena_i : IN std_logic;
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clk_i : IN std_ulogic
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clk_i : IN std_logic
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);
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);
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END fetch;
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END fetch;
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ARCHITECTURE arch OF fetch IS
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ARCHITECTURE arch OF fetch IS
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SIGNAL r, rin : fetch_out_type;
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SIGNAL r, rin : fetch_out_type;
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BEGIN
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BEGIN
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fetch_o.program_counter <= r.program_counter;
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fetch_o.program_counter <= r.program_counter;
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imem_o.adr_o <= rin.program_counter;
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imem_o.adr_o <= rin.program_counter;
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imem_o.ena_o <= ena_i;
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imem_o.ena_o <= ena_i;
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fetch_comb: PROCESS(fetch_i, r, rst_i)
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fetch_comb: PROCESS(fetch_i, r, rst_i)
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VARIABLE v : fetch_out_type;
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VARIABLE v : fetch_out_type;
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BEGIN
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BEGIN
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v := r;
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v := r;
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IF fetch_i.hazard = '1' THEN
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IF fetch_i.hazard = '1' THEN
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v.program_counter := r.program_counter;
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v.program_counter := r.program_counter;
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ELSIF fetch_i.branch = '1' THEN
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ELSIF fetch_i.branch = '1' THEN
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v.program_counter := fetch_i.branch_target;
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v.program_counter := fetch_i.branch_target;
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ELSE
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ELSE
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v.program_counter := increment(r.program_counter(CFG_IMEM_SIZE - 1 DOWNTO 2)) & "00";
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v.program_counter := increment(r.program_counter(CFG_IMEM_SIZE - 1 DOWNTO 2)) & "00";
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END IF;
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END IF;
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rin <= v;
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rin <= v;
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END PROCESS;
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END PROCESS;
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fetch_seq: PROCESS(clk_i)
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fetch_seq: PROCESS(clk_i)
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BEGIN
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BEGIN
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IF rising_edge(clk_i) THEN
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IF rising_edge(clk_i) THEN
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IF rst_i = '1' THEN
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IF rst_i = '1' THEN
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r.program_counter <= (OTHERS => '0');
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r.program_counter <= (OTHERS => '0');
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ELSIF ena_i = '1' THEN
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ELSIF ena_i = '1' THEN
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r <= rin;
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r <= rin;
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END IF;
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END IF;
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END IF;
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END IF;
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END PROCESS;
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END PROCESS;
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END arch;
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END arch;
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