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--
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--
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-- Input file : mem.vhd
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-- Input file : mem.vhd
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-- Design name : mem
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-- Design name : mem
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-- Author : Tamar Kranenburg
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-- Author : Tamar Kranenburg
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-- Company : Delft University of Technology
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-- Company : Delft University of Technology
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-- : Faculty EEMCS, Department ME&CE
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-- : Faculty EEMCS, Department ME&CE
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-- : Systems and Circuits group
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-- : Systems and Circuits group
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--
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--
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-- Description : Memory retrieves data words from a data memory. Memory file
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-- Description : Memory retrieves data words from a data memory. Memory file
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-- access of byte, halfword and word sizes is supported. The sel_o
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-- access of byte, halfword and word sizes is supported. The sel_o
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-- signal indicates which bytes should be read or written. The
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-- signal indicates which bytes should be read or written. The
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-- responsibility for writing the right memory address is not within
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-- responsibility for writing the right memory address is not within
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-- this integer unit but should be handled by the external memory
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-- this integer unit but should be handled by the external memory
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-- device. This facilitates the addition of devices with different
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-- device. This facilitates the addition of devices with different
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-- bus sizes.
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-- bus sizes.
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--
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--
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-- The dmem_i signals are directly connected to the decode and
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-- The dmem_i signals are directly connected to the decode and
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-- execute components.
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-- execute components.
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--
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--
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LIBRARY ieee;
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library ieee;
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USE ieee.std_logic_1164.ALL;
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use ieee.std_logic_1164.all;
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USE ieee.std_logic_unsigned.ALL;
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use ieee.std_logic_unsigned.all;
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LIBRARY mblite;
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library mblite;
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USE mblite.config_Pkg.ALL;
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use mblite.config_Pkg.all;
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USE mblite.core_Pkg.ALL;
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use mblite.core_Pkg.all;
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USE mblite.std_Pkg.ALL;
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use mblite.std_Pkg.all;
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ENTITY mem IS PORT
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entity mem is port
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(
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(
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mem_o : OUT mem_out_type;
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mem_o : out mem_out_type;
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dmem_o : OUT dmem_out_type;
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dmem_o : out dmem_out_type;
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mem_i : IN mem_in_type;
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mem_i : in mem_in_type;
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ena_i : IN std_logic;
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ena_i : in std_logic;
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rst_i : IN std_logic;
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rst_i : in std_logic;
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clk_i : IN std_logic
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clk_i : in std_logic
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);
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);
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END mem;
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end mem;
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ARCHITECTURE arch OF mem IS
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architecture arch of mem is
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SIGNAL r, rin : mem_out_type;
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signal r, rin : mem_out_type;
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SIGNAL mem_result : std_logic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
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signal mem_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
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BEGIN
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begin
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-- connect pipline signals
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-- connect pipline signals
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mem_o.ctrl_wb <= r.ctrl_wb;
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mem_o.ctrl_wrb <= r.ctrl_wrb;
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mem_o.ctrl_mem_wb <= r.ctrl_mem_wb;
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mem_o.ctrl_mem_wrb <= r.ctrl_mem_wrb;
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mem_o.alu_result <= r.alu_result;
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mem_o.alu_result <= r.alu_result;
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-- connect memory interface signals
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-- connect memory interface signals
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dmem_o.dat_o <= mem_result;
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dmem_o.dat_o <= mem_result;
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dmem_o.sel_o <= decode_mem_store(mem_i.alu_result(1 DOWNTO 0), mem_i.ctrl_mem.transfer_size);
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dmem_o.sel_o <= decode_mem_store(mem_i.alu_result(1 downto 0), mem_i.ctrl_mem.transfer_size);
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dmem_o.we_o <= mem_i.ctrl_mem.mem_write;
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dmem_o.we_o <= mem_i.ctrl_mem.mem_write;
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dmem_o.adr_o <= mem_i.alu_result(CFG_DMEM_SIZE - 1 DOWNTO 0);
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dmem_o.adr_o <= mem_i.alu_result(CFG_DMEM_SIZE - 1 downto 0);
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dmem_o.ena_o <= mem_i.ctrl_mem.mem_read OR mem_i.ctrl_mem.mem_write;
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dmem_o.ena_o <= mem_i.ctrl_mem.mem_read or mem_i.ctrl_mem.mem_write;
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mem_comb: PROCESS(mem_i, mem_i.ctrl_wb, mem_i.ctrl_mem, r, r.ctrl_wb, r.ctrl_mem_wb)
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mem_comb: process(mem_i, mem_i.ctrl_wrb, mem_i.ctrl_mem, r, r.ctrl_wrb, r.ctrl_mem_wrb)
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VARIABLE v : mem_out_type;
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variable v : mem_out_type;
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VARIABLE intermediate : std_logic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
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variable intermediate : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
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BEGIN
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begin
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v := r;
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v := r;
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v.ctrl_wb := mem_i.ctrl_wb;
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v.ctrl_wrb := mem_i.ctrl_wrb;
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IF mem_i.branch = '1' THEN
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if mem_i.branch = '1' then
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-- set alu result for branch and load instructions
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-- set alu result for branch and load instructions
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v.alu_result := sign_extend(mem_i.program_counter, '0', 32);
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v.alu_result := sign_extend(mem_i.program_counter, '0', 32);
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ELSE
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else
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v.alu_result := mem_i.alu_result;
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v.alu_result := mem_i.alu_result;
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END IF;
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end if;
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-- Forward memory result
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-- Forward memory result
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IF CFG_MEM_FWD_WB = true AND ( r.ctrl_mem_wb.mem_read AND compare(mem_i.ctrl_wb.reg_d, r.ctrl_wb.reg_d)) = '1' THEN
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if CFG_MEM_FWD_WRB = true and ( r.ctrl_mem_wrb.mem_read and compare(mem_i.ctrl_wrb.reg_d, r.ctrl_wrb.reg_d)) = '1' then
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intermediate := align_mem_load(mem_i.mem_result, r.ctrl_mem_wb.transfer_size, r.alu_result(1 DOWNTO 0));
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intermediate := align_mem_load(mem_i.mem_result, r.ctrl_mem_wrb.transfer_size, r.alu_result(1 downto 0));
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mem_result <= align_mem_store(intermediate, mem_i.ctrl_mem.transfer_size);
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mem_result <= align_mem_store(intermediate, mem_i.ctrl_mem.transfer_size);
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ELSE
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else
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mem_result <= mem_i.dat_d;
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mem_result <= mem_i.dat_d;
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END IF;
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end if;
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v.ctrl_mem_wb.mem_read := mem_i.ctrl_mem.mem_read;
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v.ctrl_mem_wrb.mem_read := mem_i.ctrl_mem.mem_read;
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v.ctrl_mem_wb.transfer_size := mem_i.ctrl_mem.transfer_size;
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v.ctrl_mem_wrb.transfer_size := mem_i.ctrl_mem.transfer_size;
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rin <= v;
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rin <= v;
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END PROCESS;
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end process;
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mem_seq: PROCESS(clk_i)
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mem_seq: process(clk_i)
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PROCEDURE proc_mem_reset IS
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procedure proc_mem_reset is
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BEGIN
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begin
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r.alu_result <= (OTHERS => '0');
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r.alu_result <= (others => '0');
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r.ctrl_wb.reg_d <= (OTHERS => '0');
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r.ctrl_wrb.reg_d <= (others => '0');
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r.ctrl_wb.reg_write <= '0';
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r.ctrl_wrb.reg_write <= '0';
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r.ctrl_mem_wb.mem_read <= '0';
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r.ctrl_mem_wrb.mem_read <= '0';
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r.ctrl_mem_wb.transfer_size <= WORD;
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r.ctrl_mem_wrb.transfer_size <= WORD;
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END PROCEDURE proc_mem_reset;
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end procedure proc_mem_reset;
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BEGIN
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begin
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IF rising_edge(clk_i) THEN
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if rising_edge(clk_i) then
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IF rst_i = '1' THEN
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if rst_i = '1' then
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proc_mem_reset;
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proc_mem_reset;
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ELSIF ena_i = '1' THEN
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elsif ena_i = '1' then
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r <= rin;
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r <= rin;
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END IF;
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end if;
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END IF;
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end if;
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END PROCESS;
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end process;
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END arch;
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end arch;
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No newline at end of file
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No newline at end of file
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