URL
https://opencores.org/ocsvn/mblite/mblite/trunk
[/] [mblite/] [trunk/] [sw/] [util/] [bin2vhd_4x8b.c] - Diff between revs 7 and 9
Show entire file |
Details |
Blame |
View Log
| Rev 7 |
Rev 9 |
| Line 162... |
Line 162... |
di3 <= dat_i( WIDTH_g/4 -1 DOWNTO 0);\n\
|
di3 <= dat_i( WIDTH_g/4 -1 DOWNTO 0);\n\
|
di2 <= dat_i( WIDTH_g/2 -1 DOWNTO WIDTH_g/4);\n\
|
di2 <= dat_i( WIDTH_g/2 -1 DOWNTO WIDTH_g/4);\n\
|
di1 <= dat_i(3*WIDTH_g/4 -1 DOWNTO WIDTH_g/2);\n\
|
di1 <= dat_i(3*WIDTH_g/4 -1 DOWNTO WIDTH_g/2);\n\
|
di0 <= dat_i( WIDTH_g -1 DOWNTO 3*WIDTH_g/4);\n\
|
di0 <= dat_i( WIDTH_g -1 DOWNTO 3*WIDTH_g/4);\n\
|
\n\
|
\n\
|
do3 <= ram3(TO_INTEGER(UNSIGNED(adr_i)));\n\
|
|
do2 <= ram2(TO_INTEGER(UNSIGNED(adr_i)));\n\
|
|
do1 <= ram1(TO_INTEGER(UNSIGNED(adr_i)));\n\
|
|
do0 <= ram0(TO_INTEGER(UNSIGNED(adr_i)));\n\
|
|
\n\
|
|
PROCESS(clk_i)\n\
|
PROCESS(clk_i)\n\
|
BEGIN\n\
|
BEGIN\n\
|
-- wre: 3 downto 0, while di0..di3 in byte reversed format\n\
|
-- wre: 3 downto 0, while di0..di3 in byte reversed format\n\
|
IF RISING_EDGE(clk_i) THEN\n\
|
IF RISING_EDGE(clk_i) THEN\n\
|
IF ena_i = '1' THEN\n\
|
IF ena_i = '1' THEN\n\
|
| Line 184... |
Line 179... |
ram1(TO_INTEGER(UNSIGNED(adr_i))) <= di1;\n\
|
ram1(TO_INTEGER(UNSIGNED(adr_i))) <= di1;\n\
|
END IF;\n\
|
END IF;\n\
|
IF wre_i(3) = '1' THEN\n\
|
IF wre_i(3) = '1' THEN\n\
|
ram0(TO_INTEGER(UNSIGNED(adr_i))) <= di0;\n\
|
ram0(TO_INTEGER(UNSIGNED(adr_i))) <= di0;\n\
|
END IF;\n\
|
END IF;\n\
|
|
do3 <= ram3(TO_INTEGER(UNSIGNED(adr_i)));\n\
|
|
do2 <= ram2(TO_INTEGER(UNSIGNED(adr_i)));\n\
|
|
do1 <= ram1(TO_INTEGER(UNSIGNED(adr_i)));\n\
|
|
do0 <= ram0(TO_INTEGER(UNSIGNED(adr_i)));\n\
|
END IF;\n\
|
END IF;\n\
|
END IF;\n\
|
END IF;\n\
|
END PROCESS;\n\
|
END PROCESS;\n\
|
\n\
|
\n\
|
END ARCHITECTURE arch;\n\
|
END ARCHITECTURE arch;\n\
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.