/*******************************************************************************
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/*******************************************************************************
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*
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*
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* File: bin2vhd_4x8b.c
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* File: bin2vhd_4x8b.c
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* Description: Converts a 32-bit big endian .bin file into a VHDL description
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* Description: Converts a 32-bit big endian .bin file into a VHDL description
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* containing 4 initialized 8-bit RAM instances to be used with
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* containing 4 initialized 8-bit RAM instances to be used with
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* the mbLite (ram0 containing the msb's, ram3 the lsb's).
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* the mbLite (ram0 containing the msb's, ram3 the lsb's).
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* Syntax: bin2vhd_4x8b INFILENAME OUTFILENAME ABITS
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* Syntax: bin2vhd_4x8b INFILENAME OUTFILENAME ABITS
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* with ABITS representing the number of address bits
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* with ABITS representing the number of address bits
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* ( equal to ceil(log2(MEMORY DEPTH)) ).
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* ( equal to ceil(log2(MEMORY DEPTH)) ).
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*
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*
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* Author: Rene van Leuken, edited and extended by Huib
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* Author: Rene van Leuken, edited and extended by Huib
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* Date: this version, February 2010
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* Date: this version, February 2010
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*
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*
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* Note: No checks, e.g. on inputfile being a multiple of 4 bytes
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* Note: No checks, e.g. on inputfile being a multiple of 4 bytes
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*
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*
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********************************************************************************/
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********************************************************************************/
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#include <stdio.h>
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#include <stdio.h>
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#include <string.h>
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#include <string.h>
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unsigned power (unsigned base, unsigned n) {
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unsigned power (unsigned base, unsigned n) {
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unsigned p;
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unsigned p;
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for( p = 1; n > 0; --n)
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for( p = 1; n > 0; --n)
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p = p*base;
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p = p*base;
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return p;
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return p;
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}
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}
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void print_help(char * name)
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void print_help(char * name)
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{
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{
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fprintf(stderr, "%s converts a binary file into a VHDL ram file\n", name);
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fprintf(stderr, "%s converts a binary file into a VHDL ram file\n", name);
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fprintf(stderr, "Usage: %s INFILE OUTFILE ABITS\n", name);
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fprintf(stderr, "Usage: %s INFILE OUTFILE ABITS\n", name);
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fprintf(stderr, "where ABITS (number of address bits) is log2(MEMORY DEPTH)\n");
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fprintf(stderr, "where ABITS (number of address bits) is log2(MEMORY DEPTH)\n");
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}
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}
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int main(int argc, char *argv[]) {
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int main(int argc, char *argv[]) {
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FILE *infile, *outfile;
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FILE *infile, *outfile;
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int c[4], insize;
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int c[4], insize;
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unsigned ram_size;
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unsigned ram_size;
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unsigned i = 0;
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unsigned i = 0;
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unsigned m = 0;
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unsigned m = 0;
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if (argc != 4) {
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if (argc != 4) {
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print_help(argv[0]);
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print_help(argv[0]);
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return(1);
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return(1);
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}
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}
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infile = fopen(argv[1], "rb");
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infile = fopen(argv[1], "rb");
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if (!infile) {
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if (!infile) {
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printf("Cannot open file %s\n", argv[1]);
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printf("Cannot open file %s\n", argv[1]);
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return(1);
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return(1);
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}
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}
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outfile = fopen(argv[2], "w");
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outfile = fopen(argv[2], "w");
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if (!outfile) {
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if (!outfile) {
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printf("Cannot open file %s\n", argv[2]);
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printf("Cannot open file %s\n", argv[2]);
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return(1);
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return(1);
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}
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}
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if (strlen(argv[3]) <= 0) {
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if (strlen(argv[3]) <= 0) {
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printf("Argument ABITS missing", argv[3]);
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printf("Argument ABITS missing", argv[3]);
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return(1);
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return(1);
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}
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}
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ram_size = power(2, atoi(argv[3])) * 1;
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ram_size = power(2, atoi(argv[3])) * 1;
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// determine the size of the input file in bytes
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// determine the size of the input file in bytes
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fseek(infile, 0, SEEK_END);
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fseek(infile, 0, SEEK_END);
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insize = ftell(infile);
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insize = ftell(infile);
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rewind(infile);
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rewind(infile);
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if (insize/4 > ram_size) {
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if (insize/4 > ram_size) {
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printf("RAM size (%d words) too small (at least %d words needed",
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printf("RAM size (%d words) too small (at least %d words needed",
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ram_size, insize/4);
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ram_size, insize/4);
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return(1);
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return(1);
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}
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}
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fprintf(outfile,"\
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fprintf(outfile,"\
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--------------------------------------------------------------------------------\n\
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--------------------------------------------------------------------------------\n\
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--\n\
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--\n\
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-- Filename : dmem4.vhd\n\
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-- Filename : dmem4.vhd\n\
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-- Entity : dmem4\n\
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-- Entity : dmem4\n\
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-- Input from : %s\n\
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-- Input from : %s\n\
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-- Description : Single Port Synchronous Random Access (Instruction) Memory\n\
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-- Description : Single Port Synchronous Random Access (Instruction) Memory\n\
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-- with 4 write enable ports.\n\
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-- with 4 write enable ports.\n\
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-- Author : Rene van Leuken, modified by Huib\n\
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-- Author : Rene van Leuken, modified by Huib\n\
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-- Company : Delft University of Technology\n\
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-- Company : Delft University of Technology\n\
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--\n\
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--\n\
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--------------------------------------------------------------------------------\n\
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--------------------------------------------------------------------------------\n\
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\n\
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\n\
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LIBRARY ieee;\n\
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LIBRARY ieee;\n\
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USE ieee.std_logic_1164.ALL;\n\
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USE ieee.std_logic_1164.ALL;\n\
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USE ieee.std_logic_unsigned.ALL;\n\
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USE ieee.std_logic_unsigned.ALL;\n\
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USE ieee.numeric_std.all;\n\
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USE ieee.numeric_std.all;\n\
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\n\n\
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\n\n\
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ENTITY dmem4 IS\n\
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ENTITY dmem4 IS\n\
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GENERIC (\n\
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GENERIC (\n\
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WIDTH_g : POSITIVE := 32;\n\
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WIDTH_g : POSITIVE := 32;\n\
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ABITS_g : POSITIVE := %s\n\
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ABITS_g : POSITIVE := %s\n\
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);\n\
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);\n\
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PORT (\n\
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PORT (\n\
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dat_o : OUT STD_LOGIC_VECTOR (WIDTH_g -1 DOWNTO 0);\n\
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dat_o : OUT STD_LOGIC_VECTOR (WIDTH_g -1 DOWNTO 0);\n\
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dat_i : IN STD_LOGIC_VECTOR (WIDTH_g -1 DOWNTO 0);\n\
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dat_i : IN STD_LOGIC_VECTOR (WIDTH_g -1 DOWNTO 0);\n\
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adr_i : IN STD_LOGIC_VECTOR (ABITS_g -1 DOWNTO 0);\n\
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adr_i : IN STD_LOGIC_VECTOR (ABITS_g -1 DOWNTO 0);\n\
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wre_i : IN STD_LOGIC_VECTOR (3 DOWNTO 0);\n\
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wre_i : IN STD_LOGIC_VECTOR (3 DOWNTO 0);\n\
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ena_i : IN STD_LOGIC;\n\
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ena_i : IN STD_LOGIC;\n\
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clk_i : IN STD_LOGIC\n\
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clk_i : IN STD_LOGIC\n\
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);\n\
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);\n\
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END dmem4;\n\
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END dmem4;\n\
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\n\n\
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\n\n\
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ARCHITECTURE arch OF dmem4 IS\n\
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ARCHITECTURE arch OF dmem4 IS\n\
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\n\
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\n\
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SIGNAL di0, di1, di2, di3 : STD_LOGIC_VECTOR (WIDTH_g/4 -1 DOWNTO 0);\n\
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SIGNAL di0, di1, di2, di3 : STD_LOGIC_VECTOR (WIDTH_g/4 -1 DOWNTO 0);\n\
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SIGNAL do0, do1, do2, do3 : STD_LOGIC_VECTOR (WIDTH_g/4 -1 DOWNTO 0);\n\
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SIGNAL do0, do1, do2, do3 : STD_LOGIC_VECTOR (WIDTH_g/4 -1 DOWNTO 0);\n\
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\n\
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\n\
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TYPE ram_type IS ARRAY (0 TO 2**ABITS_g -1) OF STD_LOGIC_VECTOR (WIDTH_g/4 -1 DOWNTO 0);\n\
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TYPE ram_type IS ARRAY (0 TO 2**ABITS_g -1) OF STD_LOGIC_VECTOR (WIDTH_g/4 -1 DOWNTO 0);\n\
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", argv[1], argv[3] );
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", argv[1], argv[3] );
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for ( m = 0; m < 4; m++ ) {
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for ( m = 0; m < 4; m++ ) {
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infile = freopen(argv[1], "rb", infile);
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infile = freopen(argv[1], "rb", infile);
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i = 0;
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i = 0;
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fprintf(outfile,"\
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fprintf(outfile,"\
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\nSIGNAL ram%d : ram_type := (", m);
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\nSIGNAL ram%d : ram_type := (", m);
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while (i < insize) {
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while (i < insize) {
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c[0] = fgetc(infile);
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c[0] = fgetc(infile);
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c[1] = fgetc(infile);
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c[1] = fgetc(infile);
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c[2] = fgetc(infile);
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c[2] = fgetc(infile);
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c[3] = fgetc(infile);
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c[3] = fgetc(infile);
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if ((i % 32) == 0 ) { fprintf(outfile,"\n "); }
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if ((i % 32) == 0 ) { fprintf(outfile,"\n "); }
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fprintf(outfile," X\"%.2X", (unsigned char) c[m] & 0x0ff);
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fprintf(outfile," X\"%.2X", (unsigned char) c[m] & 0x0ff);
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if (i < insize-4) { fprintf(outfile,"\","); }
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if (i < insize-4) { fprintf(outfile,"\","); }
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else { fprintf(outfile,"\""); }
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else { fprintf(outfile,"\""); }
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i += 4;
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i += 4;
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}
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}
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// Fill rest of ram if not full yet
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// Fill rest of ram if not full yet
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i = i/4;
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i = i/4;
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while (i < ram_size) {
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while (i < ram_size) {
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fprintf(outfile,",");
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fprintf(outfile,",");
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if ((i % 8) == 0 ) { fprintf(outfile,"\n "); }
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if ((i % 8) == 0 ) { fprintf(outfile,"\n "); }
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fprintf(outfile," X\"");
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fprintf(outfile," X\"");
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fprintf(outfile,"00");
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fprintf(outfile,"00");
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fprintf(outfile,"\"");
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fprintf(outfile,"\"");
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i++;
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i++;
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}
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}
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fprintf(outfile," );\n");
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fprintf(outfile," );\n");
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}
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}
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fprintf(outfile,"\n\
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fprintf(outfile,"\n\
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\n\
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\n\
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ATTRIBUTE syn_ramstyle : STRING;\n\
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ATTRIBUTE syn_ramstyle : STRING;\n\
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ATTRIBUTE syn_ramstyle OF ram0,ram1,ram2,ram3 : SIGNAL IS \"block_ram\";\n\
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ATTRIBUTE syn_ramstyle OF ram0,ram1,ram2,ram3 : SIGNAL IS \"block_ram\";\n\
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\n\
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\n\
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BEGIN\n\
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BEGIN\n\
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\n\
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\n\
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dat_o <= do0 & do1 & do2 & do3;\n\
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dat_o <= do0 & do1 & do2 & do3;\n\
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\n\
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\n\
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di3 <= dat_i( WIDTH_g/4 -1 DOWNTO 0);\n\
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di3 <= dat_i( WIDTH_g/4 -1 DOWNTO 0);\n\
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di2 <= dat_i( WIDTH_g/2 -1 DOWNTO WIDTH_g/4);\n\
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di2 <= dat_i( WIDTH_g/2 -1 DOWNTO WIDTH_g/4);\n\
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di1 <= dat_i(3*WIDTH_g/4 -1 DOWNTO WIDTH_g/2);\n\
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di1 <= dat_i(3*WIDTH_g/4 -1 DOWNTO WIDTH_g/2);\n\
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di0 <= dat_i( WIDTH_g -1 DOWNTO 3*WIDTH_g/4);\n\
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di0 <= dat_i( WIDTH_g -1 DOWNTO 3*WIDTH_g/4);\n\
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\n\
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\n\
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do3 <= ram3(TO_INTEGER(UNSIGNED(adr_i)));\n\
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do2 <= ram2(TO_INTEGER(UNSIGNED(adr_i)));\n\
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do1 <= ram1(TO_INTEGER(UNSIGNED(adr_i)));\n\
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do0 <= ram0(TO_INTEGER(UNSIGNED(adr_i)));\n\
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\n\
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PROCESS(clk_i)\n\
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PROCESS(clk_i)\n\
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BEGIN\n\
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BEGIN\n\
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-- wre: 3 downto 0, while di0..di3 in byte reversed format\n\
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-- wre: 3 downto 0, while di0..di3 in byte reversed format\n\
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IF RISING_EDGE(clk_i) THEN\n\
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IF RISING_EDGE(clk_i) THEN\n\
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IF ena_i = '1' THEN\n\
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IF ena_i = '1' THEN\n\
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IF wre_i(0) = '1' THEN\n\
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IF wre_i(0) = '1' THEN\n\
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ram3(TO_INTEGER(UNSIGNED(adr_i))) <= di3;\n\
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ram3(TO_INTEGER(UNSIGNED(adr_i))) <= di3;\n\
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END IF;\n\
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END IF;\n\
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IF wre_i(1) = '1' THEN\n\
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IF wre_i(1) = '1' THEN\n\
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ram2(TO_INTEGER(UNSIGNED(adr_i))) <= di2;\n\
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ram2(TO_INTEGER(UNSIGNED(adr_i))) <= di2;\n\
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END IF;\n\
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END IF;\n\
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IF wre_i(2) = '1' THEN\n\
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IF wre_i(2) = '1' THEN\n\
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ram1(TO_INTEGER(UNSIGNED(adr_i))) <= di1;\n\
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ram1(TO_INTEGER(UNSIGNED(adr_i))) <= di1;\n\
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END IF;\n\
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END IF;\n\
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IF wre_i(3) = '1' THEN\n\
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IF wre_i(3) = '1' THEN\n\
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ram0(TO_INTEGER(UNSIGNED(adr_i))) <= di0;\n\
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ram0(TO_INTEGER(UNSIGNED(adr_i))) <= di0;\n\
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END IF;\n\
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END IF;\n\
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do3 <= ram3(TO_INTEGER(UNSIGNED(adr_i)));\n\
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do2 <= ram2(TO_INTEGER(UNSIGNED(adr_i)));\n\
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do1 <= ram1(TO_INTEGER(UNSIGNED(adr_i)));\n\
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do0 <= ram0(TO_INTEGER(UNSIGNED(adr_i)));\n\
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END IF;\n\
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END IF;\n\
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END IF;\n\
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END IF;\n\
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END PROCESS;\n\
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END PROCESS;\n\
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\n\
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\n\
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END ARCHITECTURE arch;\n\
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END ARCHITECTURE arch;\n\
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\n\
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\n\
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-- [EOF]\n\
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-- [EOF]\n\
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");
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");
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fclose(infile);
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fclose(infile);
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fclose(outfile);
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fclose(outfile);
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return 0;
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return 0;
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}
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}
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