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-------------------------------------------------------------------------------
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-- Title : Memory Package
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-- Project : Memory Cores
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-------------------------------------------------------------------------------
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-- File : MEMPKG.VHD
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-- Author : Jamil Khatib <khatib@ieee.org>
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-- Organization: OpenIPCore Project
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-- Created : 2000/02/29
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-- Last update : 2000/02/29
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-- Platform :
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-- Simulators : Modelsim 5.2EE / Windows98
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-- Synthesizers: Leonardo / WindowsNT
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-- Target : Flex10K
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-------------------------------------------------------------------------------
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-- Description: Memory Package
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-------------------------------------------------------------------------------
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-- Copyright (c) 2000 Jamil Khatib
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--
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-- This VHDL design file is an open design; you can redistribute it and/or
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-- modify it and/or implement it under the terms of the Openip General Public
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-- License as it is going to be published by the OpenIPCore Organization and
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-- any coming versions of this license.
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-- You can check the draft license at
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-- http://www.openip.org/oc/license.html
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Revision Number : 1
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-- Version : 0.1
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-- Date : 29th Feb 2000
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-- Modifier : Jamil Khatib (khatib@ieee.org)
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-- Desccription : Created
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Revision Number : 2
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-- Version : 0.2
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-- Date : 29th Mar 2000
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-- Modifier : Jamil Khatib (khatib@ieee.org)
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-- Desccription : Memory components are added.
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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package mempkg is
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constant ADD_WIDTH : integer := 8; -- Address width
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constant WIDTH : integer := 4; -- Data width
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function slv_2_int (
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SLV : std_logic_vector )
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return integer;
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component dpmem2clk
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generic (
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ADD_WIDTH : integer := ADD_WIDTH; -- Address width
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WIDTH : integer := WIDTH; -- Word Width
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coretype : integer := 0); -- memory bulding block type
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port (
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Wclk : in std_logic; -- write clock
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Wen : in std_logic; -- Write Enable
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Wadd : in std_logic_vector(ADD_WIDTH -1 downto 0); -- Write Address
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Datain : in std_logic_vector(WIDTH -1 downto 0); -- Input Data
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Rclk : in std_logic; -- Read clock
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Ren : in std_logic; -- Read Enable
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Radd : in std_logic_vector(ADD_WIDTH -1 downto 0); -- Read Address
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Dataout : out std_logic_vector(WIDTH -1 downto 0)); -- Output data
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end component;
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component dpmem
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generic (ADD_WIDTH : integer := 4;
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WIDTH : integer := 8 );
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port (clk : in std_logic;
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reset : in std_logic;
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w_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
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r_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
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data_in : in std_logic_vector(WIDTH - 1 downto 0);
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data_out : out std_logic_vector(WIDTH - 1 downto 0 );
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WR : in std_logic;
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RE : in std_logic);
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end component;
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end mempkg;
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-------------------------------------------------------------------------------
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package body mempkg is
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-------------------------------------------------------------------------------
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function slv_2_int (
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SLV : std_logic_vector) -- std_logic_vector to convert
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return integer is
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variable Result : integer := 0; -- conversion result
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begin
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for i in SLV'range loop
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Result := Result * 2; -- shift the variable to left
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case SLV(i) is
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when '1' | 'H' => Result := Result + 1;
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when '0' | 'L' => Result := Result + 0;
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when others => null;
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end case;
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end loop;
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return Result;
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end;
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-------------------------------------------------------------------------------
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end mempkg;
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-------------------------------------------------------------------------------
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