--------------------------------------------------------------------------
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--------------------------------------------------------------------------
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-- --
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-- --
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-- --
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-- --
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-- miniMIPS Superscalar Processor : miniMIPS Superscalar processor --
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-- miniMIPS Superscalar Processor : miniMIPS Superscalar processor --
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-- based on miniMIPS Processor --
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-- based on miniMIPS Processor --
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-- --
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-- --
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-- --
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-- --
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-- Author : Miguel Cafruni --
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-- Author : Miguel Cafruni --
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-- miguel_cafruni@hotmail.com --
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-- miguel_cafruni@hotmail.com --
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-- December 2018 --
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-- December 2018 --
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--------------------------------------------------------------------------
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--------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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library work;
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library work;
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use work.pack_mips.all;
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use work.pack_mips.all;
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entity minimips is
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entity minimips is
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port (
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port (
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clock : in std_logic;
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clock : in std_logic;
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clock2 : in std_logic;
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clock2 : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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-- Ram connexion
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-- Ram connexion
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ram_req : out std_logic;
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ram_req : out std_logic;
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ram_adr : out bus32;
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ram_adr : out bus32;
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ram_r_w : out std_logic;
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ram_r_w : out std_logic;
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ram_data : inout bus32;
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ram_data : inout bus32;
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ram_ack : in std_logic;
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ram_ack : in std_logic;
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ram_req2 : out std_logic;
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ram_req2 : out std_logic;
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ram_adr2 : out bus32;
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ram_adr2 : out bus32;
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ram_r_w2 : out std_logic;
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ram_r_w2 : out std_logic;
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ram_data2 : inout bus32;
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ram_data2 : inout bus32;
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ram_ack2 : in std_logic;
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ram_ack2 : in std_logic;
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-- Hardware interruption
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-- Hardware interruption
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it_mat : in std_logic
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it_mat : in std_logic
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);
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);
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end minimips;
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end minimips;
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architecture rtl of minimips is
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architecture rtl of minimips is
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-- General signals
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-- General signals
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signal stop_all : std_logic; -- Lock the pipeline evolution
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signal stop_all : std_logic; -- Lock the pipeline evolution
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signal stop_all2 : std_logic; -- Lock the pipeline evolution
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signal stop_all2 : std_logic; -- Lock the pipeline evolution
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signal it_mat_clk : std_logic; -- Synchronised hardware interruption
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signal it_mat_clk : std_logic; -- Synchronised hardware interruption
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signal stop_pf : std_logic; -- Lock the pc
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signal stop_pf : std_logic; -- Lock the pc
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signal stop_pf2 : std_logic; -- Lock the pc
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signal stop_pf2 : std_logic; -- Lock the pc
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signal genop : std_logic; -- envoi de nops
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signal genop : std_logic; -- envoi de nops
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signal genop2 : std_logic; -- envoi de nops
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signal genop2 : std_logic; -- envoi de nops
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signal clock_out1, clock_out2 : std_logic; -- sem uso atual
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-- interface PF - EI
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-- interface PF - EI
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signal PF_pc : bus32; -- PC value
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signal PF_pc : bus32; -- PC value
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signal PF_pc_4 : bus32;
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signal PF_pc_4 : bus32;
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-- interface Controler - EI
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-- interface Controler - EI
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signal CTE_instr : bus32; -- Instruction from the memory
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signal CTE_instr : bus32; -- Instruction from the memory
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signal ETC_adr : bus32; -- Address to read in memory
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signal ETC_adr : bus32; -- Address to read in memory
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-- interface Controler - EI2
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-- interface Controler - EI2
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signal CTE_instr2 : bus32; -- Instruction from the memory
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signal CTE_instr2 : bus32; -- Instruction from the memory
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signal ETC_adr2 : bus32; -- Address to read in memory
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signal ETC_adr2 : bus32; -- Address to read in memory
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-- interface EI - DI
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-- interface EI - DI
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signal EI_instr : bus32; -- Read interface
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signal EI_instr : bus32; -- Read interface
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signal EI_adr : bus32; -- Address from the read instruction
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signal EI_adr : bus32; -- Address from the read instruction
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signal EI_it_ok : std_logic; -- Allow hardware interruptions
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signal EI_it_ok : std_logic; -- Allow hardware interruptions
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-- interface EI2 - DI2
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-- interface EI2 - DI2
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signal EI_instr2 : bus32; -- Read interface
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signal EI_instr2 : bus32; -- Read interface
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signal EI_adr2 : bus32; -- Address from the read instruction
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signal EI_adr2 : bus32; -- Address from the read instruction
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signal EI_it_ok2 : std_logic; -- Allow hardware interruptions
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signal EI_it_ok2 : std_logic; -- Allow hardware interruptions
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-- DI output
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-- DI output
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signal bra_detect : std_logic; -- Branch detection in the current instruction
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signal bra_detect : std_logic; -- Branch detection in the current instruction
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-- DI2 output
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-- DI2 output
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signal bra_detect2 : std_logic; -- Branch detection in the current instruction
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signal bra_detect2 : std_logic; -- Branch detection in the current instruction
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-- Asynchronous connexion with the bypass unit
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-- Asynchronous connexion with the bypass unit
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signal adr_reg1 : adr_reg_type; -- Operand 1 address
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signal adr_reg1 : adr_reg_type; -- Operand 1 address
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signal adr_reg2 : adr_reg_type; -- Operand 2 address
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signal adr_reg2 : adr_reg_type; -- Operand 2 address
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signal use1 : std_logic; -- Operand 1 utilisation
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signal use1 : std_logic; -- Operand 1 utilisation
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signal use2 : std_logic; -- Operand 2 utilisation
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signal use2 : std_logic; -- Operand 2 utilisation
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signal data1 : bus32; -- First register value
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signal data1 : bus32; -- First register value
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signal data2 : bus32; -- Second register value
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signal data2 : bus32; -- Second register value
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signal alea : std_logic; -- Unresolved hazards detected
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signal alea : std_logic; -- Unresolved hazards detected
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-- Asynchronous connexion with the bypass unit
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-- Asynchronous connexion with the bypass unit
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signal adr_reg3 : adr_reg_type; -- Operand 1 address
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signal adr_reg3 : adr_reg_type; -- Operand 1 address
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signal adr_reg4 : adr_reg_type; -- Operand 2 address
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signal adr_reg4 : adr_reg_type; -- Operand 2 address
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signal use3 : std_logic; -- Operand 3 utilisation
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signal use3 : std_logic; -- Operand 3 utilisation
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signal use4 : std_logic; -- Operand 4 utilisation
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signal use4 : std_logic; -- Operand 4 utilisation
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signal data3 : bus32; -- 3th register value
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signal data3 : bus32; -- 3th register value
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signal data4 : bus32; -- 4th register value
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signal data4 : bus32; -- 4th register value
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signal alea2 : std_logic; -- Unresolved hazards detected 2nd pipe
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signal alea2 : std_logic; -- Unresolved hazards detected 2nd pipe
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-- interface DI - EX
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-- interface DI - EX
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signal DI_bra : std_logic; -- Branch decoded
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signal DI_bra : std_logic; -- Branch decoded
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signal DI_link : std_logic; -- A link for that instruction
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signal DI_link : std_logic; -- A link for that instruction
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signal DI_op1 : bus32; -- operand 1 for alu
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signal DI_op1 : bus32; -- operand 1 for alu
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signal DI_op2 : bus32; -- operand 2 for alu
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signal DI_op2 : bus32; -- operand 2 for alu
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signal DI_code_ual : alu_ctrl_type; -- Alu operation
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signal DI_code_ual : alu_ctrl_type; -- Alu operation
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signal DI_offset : bus32; -- Offset for the address calculation
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signal DI_offset : bus32; -- Offset for the address calculation
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signal DI_adr_reg_dest : adr_reg_type; -- Address of the destination register of the result
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signal DI_adr_reg_dest : adr_reg_type; -- Address of the destination register of the result
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signal DI_ecr_reg : std_logic; -- Effective writing of the result
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signal DI_ecr_reg : std_logic; -- Effective writing of the result
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signal DI_mode : std_logic; -- Address mode (relative to pc or indexed to a register)
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signal DI_mode : std_logic; -- Address mode (relative to pc or indexed to a register)
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signal DI_op_mem : std_logic; -- Memory operation request
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signal DI_op_mem : std_logic; -- Memory operation request
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signal DI_r_w : std_logic; -- Type of memory operation (reading or writing)
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signal DI_r_w : std_logic; -- Type of memory operation (reading or writing)
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signal DI_adr : bus32; -- Address of the decoded instruction
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signal DI_adr : bus32; -- Address of the decoded instruction
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signal DI_exc_cause : bus32; -- Potential exception detected
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signal DI_exc_cause : bus32; -- Potential exception detected
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signal DI_level : level_type; -- Availability of the result for the data bypass
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signal DI_level : level_type; -- Availability of the result for the data bypass
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signal DI_it_ok : std_logic; -- Allow hardware interruptions
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signal DI_it_ok : std_logic; -- Allow hardware interruptions
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-- interface DI2 - EX2
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-- interface DI2 - EX2
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signal DI_bra2 : std_logic; -- Branch decoded
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signal DI_bra2 : std_logic; -- Branch decoded
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signal DI_link2 : std_logic; -- A link for that instruction
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signal DI_link2 : std_logic; -- A link for that instruction
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signal DI_op3 : bus32; -- operand 1 for alu 2
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signal DI_op3 : bus32; -- operand 1 for alu 2
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signal DI_op4 : bus32; -- operand 2 for alu 2
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signal DI_op4 : bus32; -- operand 2 for alu 2
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signal DI_code_ual2 : alu_ctrl_type; -- Alu operation
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signal DI_code_ual2 : alu_ctrl_type; -- Alu operation
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signal DI_offset2 : bus32; -- Offset for the address calculation
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signal DI_offset2 : bus32; -- Offset for the address calculation
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signal DI_adr_reg_dest2 : adr_reg_type; -- Address of the destination register of the result
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signal DI_adr_reg_dest2 : adr_reg_type; -- Address of the destination register of the result
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signal DI_ecr_reg2 : std_logic; -- Effective writing of the result
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signal DI_ecr_reg2 : std_logic; -- Effective writing of the result
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signal DI_mode2 : std_logic; -- Address mode (relative to pc or indexed to a register)
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signal DI_mode2 : std_logic; -- Address mode (relative to pc or indexed to a register)
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signal DI_op_mem2 : std_logic; -- Memory operation request
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signal DI_op_mem2 : std_logic; -- Memory operation request
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signal DI_r_w2 : std_logic; -- Type of memory operation (reading or writing)
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signal DI_r_w2 : std_logic; -- Type of memory operation (reading or writing)
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signal DI_adr2 : bus32; -- Address of the decoded instruction
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signal DI_adr2 : bus32; -- Address of the decoded instruction
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signal DI_exc_cause2 : bus32; -- Potential exception detected
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signal DI_exc_cause2 : bus32; -- Potential exception detected
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signal DI_level2 : level_type; -- Availability of the result for the data bypass
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signal DI_level2 : level_type; -- Availability of the result for the data bypass
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signal DI_it_ok2 : std_logic; -- Allow hardware interruptions
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signal DI_it_ok2 : std_logic; -- Allow hardware interruptions
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-- interface EX - MEM
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-- interface EX - MEM
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signal EX_adr : bus32; -- Instruction address
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signal EX_adr : bus32; -- Instruction address
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signal EX_bra_confirm : std_logic; -- Branch execution confirmation
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signal EX_bra_confirm : std_logic; -- Branch execution confirmation
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signal EX_data_ual : bus32; -- Ual result
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signal EX_data_ual : bus32; -- Ual result
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signal EX_adresse : bus32; -- Address calculation result
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signal EX_adresse : bus32; -- Address calculation result
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signal ex_adresse_p1p2_s : bus32; -- resultado do calculo do endereco do desvio + 4 para pipe 2
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signal ex_adresse_p1p2_s : bus32; -- resultado do calculo do endereco do desvio + 4 para pipe 2
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signal EX_adr_reg_dest : adr_reg_type; -- Destination register for the result
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signal EX_adr_reg_dest : adr_reg_type; -- Destination register for the result
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signal EX_ecr_reg : std_logic; -- Effective writing of the result
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signal EX_ecr_reg : std_logic; -- Effective writing of the result
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signal EX_op_mem : std_logic; -- Memory operation needed
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signal EX_op_mem : std_logic; -- Memory operation needed
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signal EX_r_w : std_logic; -- Type of memory operation (read or write)
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signal EX_r_w : std_logic; -- Type of memory operation (read or write)
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signal EX_exc_cause : bus32; -- Potential cause exception
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signal EX_exc_cause : bus32; -- Potential cause exception
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signal EX_level : level_type; -- Availability stage of result for bypassing
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signal EX_level : level_type; -- Availability stage of result for bypassing
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signal EX_it_ok : std_logic; -- Allow hardware interruptions
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signal EX_it_ok : std_logic; -- Allow hardware interruptions
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-- interface EX2 - MEM
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-- interface EX2 - MEM
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signal EX_adr2 : bus32; -- Instruction address
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signal EX_adr2 : bus32; -- Instruction address
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signal EX_bra_confirm2 : std_logic; -- Branch execution confirmation
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signal EX_bra_confirm2 : std_logic; -- Branch execution confirmation
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signal EX_data_ual2 : bus32; -- Ual result
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signal EX_data_ual2 : bus32; -- Ual result
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signal EX_adresse2 : bus32; -- Address calculation result
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signal EX_adresse2 : bus32; -- Address calculation result
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signal ex_adresse_p2p1_s : bus32; -- resultado do calculo do endereco do desvio + 4 para pipe 1
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signal ex_adresse_p2p1_s : bus32; -- resultado do calculo do endereco do desvio + 4 para pipe 1
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signal EX_adr_reg_dest2 : adr_reg_type; -- Destination register for the result
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signal EX_adr_reg_dest2 : adr_reg_type; -- Destination register for the result
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signal EX_ecr_reg2 : std_logic; -- Effective writing of the result
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signal EX_ecr_reg2 : std_logic; -- Effective writing of the result
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signal EX_op_mem2 : std_logic; -- Memory operation needed
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signal EX_op_mem2 : std_logic; -- Memory operation needed
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signal EX_r_w2 : std_logic; -- Type of memory operation (read or write)
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signal EX_r_w2 : std_logic; -- Type of memory operation (read or write)
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signal EX_exc_cause2 : bus32; -- Potential cause exception
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signal EX_exc_cause2 : bus32; -- Potential cause exception
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signal EX_level2 : level_type; -- Availability stage of result for bypassing
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signal EX_level2 : level_type; -- Availability stage of result for bypassing
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signal EX_it_ok2 : std_logic; -- Allow hardware interruptions
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signal EX_it_ok2 : std_logic; -- Allow hardware interruptions
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-- interface Controler - MEM
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-- interface Controler - MEM
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signal MTC_data : bus32; -- Data to write in memory
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signal MTC_data : bus32; -- Data to write in memory
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signal MTC_adr : bus32; -- Address for memory
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signal MTC_adr : bus32; -- Address for memory
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signal MTC_r_w : std_logic; -- Read/Write in memory
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signal MTC_r_w : std_logic; -- Read/Write in memory
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signal MTC_req : std_logic; -- Request access to memory
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signal MTC_req : std_logic; -- Request access to memory
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signal CTM_data : bus32; -- Data from memory
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signal CTM_data : bus32; -- Data from memory
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-- interface Controler2 - MEM
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-- interface Controler2 - MEM
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signal MTC_data2 : bus32; -- Data to write in memory
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signal MTC_data2 : bus32; -- Data to write in memory
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signal MTC_adr2 : bus32; -- Address for memory
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signal MTC_adr2 : bus32; -- Address for memory
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signal MTC_r_w2 : std_logic; -- Read/Write in memory
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signal MTC_r_w2 : std_logic; -- Read/Write in memory
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signal MTC_req2 : std_logic; -- Request access to memory
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signal MTC_req2 : std_logic; -- Request access to memory
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signal CTM_data2 : bus32; -- Data from memory
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signal CTM_data2 : bus32; -- Data from memory
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-- interface MEM - REG
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-- interface MEM - REG
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signal MEM_adr : bus32; -- Instruction address
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signal MEM_adr : bus32; -- Instruction address
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signal MEM_adr_reg_dest : adr_reg_type; -- Destination register address
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signal MEM_adr_reg_dest : adr_reg_type; -- Destination register address
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signal MEM_ecr_reg : std_logic; -- Writing of the destination register
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signal MEM_ecr_reg : std_logic; -- Writing of the destination register
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signal MEM_data_ecr : bus32; -- Data to write (from alu or memory)
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signal MEM_data_ecr : bus32; -- Data to write (from alu or memory)
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signal MEM_exc_cause : bus32; -- Potential exception cause
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signal MEM_exc_cause : bus32; -- Potential exception cause
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signal MEM_level : level_type; -- Availability stage for the result for bypassing
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signal MEM_level : level_type; -- Availability stage for the result for bypassing
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signal MEM_it_ok : std_logic; -- Allow hardware interruptions
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signal MEM_it_ok : std_logic; -- Allow hardware interruptions
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-- connexion to the register banks
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-- connexion to the register banks
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-- Writing commands in the register banks
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-- Writing commands in the register banks
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signal write_data : bus32; -- Data to write
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signal write_data : bus32; -- Data to write
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signal write_adr : bus5; -- Address of the register to write
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signal write_adr : bus5; -- Address of the register to write
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signal write_GPR : std_logic; -- Selection in the internal registers
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signal write_GPR : std_logic; -- Selection in the internal registers
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signal write_SCP : std_logic; -- Selection in the coprocessor system registers
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signal write_SCP : std_logic; -- Selection in the coprocessor system registers
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-- Reading commands for Reading in the registers
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-- Reading commands for Reading in the registers
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signal read_adr1 : bus5; -- Address of the first register to read
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signal read_adr1 : bus5; -- Address of the first register to read
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signal read_adr2 : bus5; -- Address of the second register to read
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signal read_adr2 : bus5; -- Address of the second register to read
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signal read_data1_GPR : bus32; -- Value of operand 1 from the internal registers
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signal read_data1_GPR : bus32; -- Value of operand 1 from the internal registers
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signal read_data1_SCP : bus32; -- Value of operand 2 from the internal registers
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signal read_data1_SCP : bus32; -- Value of operand 2 from the internal registers
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signal read_data2_GPR : bus32; -- Value of operand 1 from the coprocessor system registers
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signal read_data2_GPR : bus32; -- Value of operand 1 from the coprocessor system registers
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signal read_data2_SCP : bus32; -- Value of operand 2 from the coprocessor system registers
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signal read_data2_SCP : bus32; -- Value of operand 2 from the coprocessor system registers
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-- interface MEM - REG duplicado as entradas e saidas do REG
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-- interface MEM - REG duplicado as entradas e saidas do REG
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signal MEM_adr2 : bus32; -- Instruction address
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signal MEM_adr2 : bus32; -- Instruction address
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signal MEM_adr_reg_dest2 : adr_reg_type; -- Destination register address
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signal MEM_adr_reg_dest2 : adr_reg_type; -- Destination register address
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signal MEM_ecr_reg2 : std_logic; -- Writing of the destination register
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signal MEM_ecr_reg2 : std_logic; -- Writing of the destination register
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signal MEM_data_ecr2 : bus32; -- Data to write (from alu or memory)
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signal MEM_data_ecr2 : bus32; -- Data to write (from alu or memory)
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signal MEM_exc_cause2 : bus32; -- Potential exception cause
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signal MEM_exc_cause2 : bus32; -- Potential exception cause
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signal MEM_level2 : level_type; -- Availability stage for the result for bypassing
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signal MEM_level2 : level_type; -- Availability stage for the result for bypassing
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signal MEM_it_ok2 : std_logic; -- Allow hardware interruptions
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signal MEM_it_ok2 : std_logic; -- Allow hardware interruptions
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-- connexion to the register banks
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-- connexion to the register banks
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-- Writing commands in the register banks
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-- Writing commands in the register banks
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signal write_data2 : bus32; -- Data to write
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signal write_data2 : bus32; -- Data to write
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signal write_adr2 : bus5; -- Address of the register to write
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signal write_adr2 : bus5; -- Address of the register to write
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signal write_GPR2 : std_logic; -- Selection in the internal registers
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signal write_GPR2 : std_logic; -- Selection in the internal registers
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--signal write_SCP2 : std_logic; -- Selection in the coprocessor system registers
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--signal write_SCP2 : std_logic; -- Selection in the coprocessor system registers
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-- Reading commands for Reading in the registers
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-- Reading commands for Reading in the registers
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signal read_adr3 : bus5; -- Address of the first register to read
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signal read_adr3 : bus5; -- Address of the first register to read
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signal read_adr4 : bus5; -- Address of the second register to read
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signal read_adr4 : bus5; -- Address of the second register to read
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signal read_data3_GPR : bus32; -- Value of operand 1 from the internal registers
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signal read_data3_GPR : bus32; -- Value of operand 1 from the internal registers
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signal read_data3_SCP : bus32; -- Value of operand 2 from the internal registers
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signal read_data3_SCP : bus32; -- Value of operand 2 from the internal registers
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signal read_data4_GPR : bus32; -- Value of operand 1 from the coprocessor system registers
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signal read_data4_GPR : bus32; -- Value of operand 1 from the coprocessor system registers
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signal read_data4_SCP : bus32; -- Value of operand 2 from the coprocessor system registers
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signal read_data4_SCP : bus32; -- Value of operand 2 from the coprocessor system registers
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-- Interruption controls
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-- Interruption controls
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signal interrupt : std_logic; -- Interruption to take into account
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signal interrupt : std_logic; -- Interruption to take into account
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signal vecteur_it : bus32; -- Interruption vector
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signal vecteur_it : bus32; -- Interruption vector
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-- Sinais atrasados meio ciclo
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-- Sinais atrasados meio ciclo
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signal DI_bra_D : std_logic;
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signal DI_bra_D : std_logic;
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signal bra_detect_D : std_logic;
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signal bra_detect_D : std_logic;
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signal EX_bra_confirm_D : std_logic;
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signal EX_bra_confirm_D : std_logic;
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signal alea_D : std_logic;
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signal alea_D : std_logic;
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signal alea2_D : std_logic;
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signal alea2_D : std_logic;
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signal EX_bra_confirm2_D : std_logic;
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signal EX_bra_confirm2_D : std_logic;
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signal bra_detect2_D : std_logic;
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signal bra_detect2_D : std_logic;
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signal DI_bra2_D : std_logic;
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signal DI_bra2_D : std_logic;
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signal iload_D : bus1; -- sem uso atual
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signal iload_D : bus1; -- sem uso atual
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signal istore_D : bus1;
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signal istore_D : bus1;
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signal istore2_D : bus1;
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signal istore2_D : bus1;
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--
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--
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signal istore : bus1;
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signal istore : bus1;
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signal iload : bus1; -- sem uso atual
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signal iload : bus1; -- sem uso atual
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signal istore2 : bus1;
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signal istore2 : bus1;
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signal branch1 : std_logic;
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signal branch1 : std_logic;
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signal branch2 : std_logic;
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signal branch2 : std_logic;
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signal bra_adr_s : bus32;
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signal bra_adr_s : bus32;
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signal bra_adr2_s : bus32;
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signal bra_adr2_s : bus32;
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signal aleaEI : bus1;
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signal aleaEI : bus1;
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signal aleaDI : bus1;
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signal aleaDI : bus1;
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signal alea2EI2 : bus1;
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signal alea2EI2 : bus1;
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signal alea2DI2 : bus1;
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signal alea2DI2 : bus1;
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signal ex2_data_hilo : bus64;--resultado da multiplicacao do pieline2 14-12-18
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signal ex2_data_hilo : bus64;--resultado da multiplicacao do pieline2 14-12-18
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signal ex_data_hilo : bus64;--resultado da multiplicacao do pieline1
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signal ex_data_hilo : bus64;--resultado da multiplicacao do pieline1
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begin
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begin
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aleaEI <= alea or alea2_D;
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aleaEI <= alea or alea2_D;
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aleaDI <= alea or alea2_D;
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aleaDI <= alea or alea2_D;
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alea2EI2 <= alea2 or alea_D;
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alea2EI2 <= alea2 or alea_D;
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alea2DI2 <= alea2 or alea_D;
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alea2DI2 <= alea2 or alea_D;
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stop_pf <= DI_bra or DI_bra2_D or bra_detect or bra_detect2_D or alea or alea2_D or istore2 or istore2_D;
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stop_pf <= DI_bra or DI_bra2_D or bra_detect or bra_detect2_D or alea or alea2_D or istore2 or istore2_D;
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genop <= bra_detect or bra_detect2_D or EX_bra_confirm or EX_bra_confirm2_D or DI_bra or DI_bra2_D or istore2 or istore2_D;
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genop <= bra_detect or bra_detect2_D or EX_bra_confirm or EX_bra_confirm2_D or DI_bra or DI_bra2_D or istore2 or istore2_D;
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stop_pf2 <= DI_bra2 or DI_bra_D or bra_detect2 or bra_detect_D or alea2 or alea_D or istore or istore_D;
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stop_pf2 <= DI_bra2 or DI_bra_D or bra_detect2 or bra_detect_D or alea2 or alea_D or istore or istore_D;
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genop2 <= bra_detect2 or bra_detect_D or EX_bra_confirm2 or EX_bra_confirm_D or DI_bra2 or DI_bra_D or istore or istore_D;
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genop2 <= bra_detect2 or bra_detect_D or EX_bra_confirm2 or EX_bra_confirm_D or DI_bra2 or DI_bra_D or istore or istore_D;
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branch1 <= EX_bra_confirm or EX_bra_confirm2_D;
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branch1 <= EX_bra_confirm or EX_bra_confirm2_D;
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branch2 <= EX_bra_confirm2 or EX_bra_confirm_D;
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branch2 <= EX_bra_confirm2 or EX_bra_confirm_D;
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-- muxes para selecionar o endereco do branh apropriado 12-08-2018
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-- muxes para selecionar o endereco do branh apropriado 12-08-2018
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with EX_bra_confirm2_D select
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with EX_bra_confirm2_D select
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bra_adr_s <= ex_adresse_p2p1_s when '1',
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bra_adr_s <= ex_adresse_p2p1_s when '1',
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EX_adresse when others;
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EX_adresse when others;
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with EX_bra_confirm_D select
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with EX_bra_confirm_D select
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bra_adr2_s <= ex_adresse_p1p2_s when '1',
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bra_adr2_s <= ex_adresse_p1p2_s when '1',
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EX_adresse2 when others;
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EX_adresse2 when others;
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-- Take into account the hardware interruption on rising edge
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-- Take into account the hardware interruption on rising edge
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process (clock)
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process (clock)
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begin
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begin
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if clock='1' and clock'event then
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if clock='1' and clock'event then
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it_mat_clk <= it_mat;
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it_mat_clk <= it_mat;
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end if;
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end if;
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end process;
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end process;
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U1_pf : pps_pf port map (
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U1_pf : pps_pf port map (
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clock => clock,
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clock => clock,
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clock2 => clock2,
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clock2 => clock2,
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reset => reset,
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reset => reset,
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stop_all => stop_all, -- Unconditionnal locking of the pipeline stage
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stop_all => stop_all, -- Unconditionnal locking of the pipeline stage
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stop_all2 => stop_all2,
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stop_all2 => stop_all2,
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-- entrees asynchrones
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-- entrees asynchrones
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bra_adr => bra_adr_s,--EX_adresse, -- Branch
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bra_adr => bra_adr_s,--EX_adresse, -- Branch
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bra_cmd => branch1, -- Address to load when an effective branch
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bra_cmd => branch1, -- Address to load when an effective branch
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exch_adr => vecteur_it, -- Exception branch
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exch_adr => vecteur_it, -- Exception branch
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exch_cmd => interrupt, -- Exception vector
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exch_cmd => interrupt, -- Exception vector
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-- entrees asynchrones 24\03\18
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-- entrees asynchrones 24\03\18
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bra_adr2 => bra_adr2_s,-- EX_adresse2, -- Branch
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bra_adr2 => bra_adr2_s,-- EX_adresse2, -- Branch
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bra_cmd2 => branch2, -- Address to load when an effective branch
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bra_cmd2 => branch2, -- Address to load when an effective branch
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exch_adr2 => vecteur_it, -- Exception branch
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exch_adr2 => vecteur_it, -- Exception branch
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exch_cmd2 => interrupt, -- Exception vector
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exch_cmd2 => interrupt, -- Exception vector
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-- Lock the stage
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-- Lock the stage
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stop_pf => stop_pf,
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stop_pf => stop_pf,
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stop_pf2 => stop_pf2,--estava errado 'stop_pf' corrigido em 03-04-18
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stop_pf2 => stop_pf2,--estava errado 'stop_pf' corrigido em 03-04-18
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-- Synchronous output to EI stage
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-- Synchronous output to EI stage
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PF_pc => PF_pc, -- PC value
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PF_pc => PF_pc, -- PC value
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PF_pc_4 => PF_pc_4
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PF_pc_4 => PF_pc_4
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);
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);
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U2_ei : pps_ei port map (
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U2_ei : pps_ei port map (
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clock => clock,
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clock => clock,
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reset => reset,
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reset => reset,
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clear => interrupt, -- Clear the pipeline stage
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clear => interrupt, -- Clear the pipeline stage
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stop_all => stop_all, -- Evolution locking signal
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stop_all => stop_all, -- Evolution locking signal
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|
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-- Asynchronous inputs
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-- Asynchronous inputs
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stop_ei => aleaEI, -- Lock the EI_adr and Ei_instr registers
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stop_ei => aleaEI, -- Lock the EI_adr and Ei_instr registers
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genop => genop, -- Send nops
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genop => genop, -- Send nops
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|
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-- interface Controler - EI
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-- interface Controler - EI
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CTE_instr => CTE_instr, -- Instruction from the memory
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CTE_instr => CTE_instr, -- Instruction from the memory
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ETC_adr => ETC_adr, -- Address to read in memory
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ETC_adr => ETC_adr, -- Address to read in memory
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|
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-- Synchronous inputs from PF stage
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-- Synchronous inputs from PF stage
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PF_pc => PF_pc, -- Current value of the pc
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PF_pc => PF_pc, -- Current value of the pc
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|
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-- Synchronous outputs to DI stage
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-- Synchronous outputs to DI stage
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EI_instr => EI_instr, -- Read interface
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EI_instr => EI_instr, -- Read interface
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EI_adr => EI_adr, -- Address from the read instruction
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EI_adr => EI_adr, -- Address from the read instruction
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EI_it_ok => EI_it_ok -- Allow hardware interruptions
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EI_it_ok => EI_it_ok -- Allow hardware interruptions
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);
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);
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U3_di : pps_di port map (
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U3_di : pps_di port map (
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clock => clock,
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clock => clock,
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reset => reset,
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reset => reset,
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stop_all => stop_all, -- Unconditionnal locking of the outputs
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stop_all => stop_all, -- Unconditionnal locking of the outputs
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clear => interrupt, -- Clear the pipeline stage (nop in the outputs)
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clear => interrupt, -- Clear the pipeline stage (nop in the outputs)
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|
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-- Asynchronous outputs
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-- Asynchronous outputs
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bra_detect => bra_detect, -- Branch detection in the current instruction
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bra_detect => bra_detect, -- Branch detection in the current instruction
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|
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-- Asynchronous connexion with the register management and data bypass unit
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-- Asynchronous connexion with the register management and data bypass unit
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adr_reg1 => adr_reg1, -- Address of the first register operand
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adr_reg1 => adr_reg1, -- Address of the first register operand
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adr_reg2 => adr_reg2, -- Address of the second register operand
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adr_reg2 => adr_reg2, -- Address of the second register operand
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use1 => use1, -- Effective use of operand 1
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use1 => use1, -- Effective use of operand 1
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use2 => use2, -- Effective use of operand 2
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use2 => use2, -- Effective use of operand 2
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--iload => iload,
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--iload => iload,
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istore => istore,
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istore => istore,
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stop_di => aleaDI, -- Unresolved detected : send nop in the pipeline
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stop_di => aleaDI, -- Unresolved detected : send nop in the pipeline
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data1 => data1, -- Operand register 1
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data1 => data1, -- Operand register 1
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data2 => data2, -- Operand register 2
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data2 => data2, -- Operand register 2
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|
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-- Datas from EI stage
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-- Datas from EI stage
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EI_adr => EI_adr, -- Address of the instruction
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EI_adr => EI_adr, -- Address of the instruction
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EI_instr => EI_instr, -- The instruction to decode
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EI_instr => EI_instr, -- The instruction to decode
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EI_it_ok => EI_it_ok, -- Allow hardware interruptions
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EI_it_ok => EI_it_ok, -- Allow hardware interruptions
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|
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-- Synchronous output to EX stage
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-- Synchronous output to EX stage
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DI_bra => DI_bra, -- Branch decoded
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DI_bra => DI_bra, -- Branch decoded
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DI_link => DI_link, -- A link for that instruction
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DI_link => DI_link, -- A link for that instruction
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DI_op1 => DI_op1, -- operand 1 for alu
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DI_op1 => DI_op1, -- operand 1 for alu
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DI_op2 => DI_op2, -- operand 2 for alu
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DI_op2 => DI_op2, -- operand 2 for alu
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DI_code_ual => DI_code_ual, -- Alu operation
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DI_code_ual => DI_code_ual, -- Alu operation
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DI_offset => DI_offset, -- Offset for the address calculation
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DI_offset => DI_offset, -- Offset for the address calculation
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DI_adr_reg_dest => DI_adr_reg_dest, -- Address of the destination register of the result
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DI_adr_reg_dest => DI_adr_reg_dest, -- Address of the destination register of the result
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DI_ecr_reg => DI_ecr_reg, -- Effective writing of the result
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DI_ecr_reg => DI_ecr_reg, -- Effective writing of the result
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DI_mode => DI_mode, -- Address mode (relative to pc or indexed to a register)
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DI_mode => DI_mode, -- Address mode (relative to pc or indexed to a register)
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DI_op_mem => DI_op_mem, -- Memory operation request
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DI_op_mem => DI_op_mem, -- Memory operation request
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DI_r_w => DI_r_w, -- Type of memory operation (reading or writing)
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DI_r_w => DI_r_w, -- Type of memory operation (reading or writing)
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DI_adr => DI_adr, -- Address of the decoded instruction
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DI_adr => DI_adr, -- Address of the decoded instruction
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DI_exc_cause => DI_exc_cause, -- Potential exception detected
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DI_exc_cause => DI_exc_cause, -- Potential exception detected
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DI_level => DI_level, -- Availability of the result for the data bypass
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DI_level => DI_level, -- Availability of the result for the data bypass
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DI_it_ok => DI_it_ok -- Allow hardware interruptions
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DI_it_ok => DI_it_ok -- Allow hardware interruptions
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);
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);
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|
|
|
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U4_ex : pps_ex port map (
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U4_ex : pps_ex port map (
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clock => clock,
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clock => clock,
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clock2 => clock,
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clock2 => clock2,
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reset => reset,
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reset => reset,
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stop_all => stop_all,
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stop_all => stop_all,
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stop_all2 => stop_all2, -- Unconditionnal locking of outputs
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stop_all2 => stop_all2, -- Unconditionnal locking of outputs
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clear => interrupt, -- Clear the pipeline stage
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clear => interrupt, -- Clear the pipeline stage
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|
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-- Datas from DI stage
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-- Datas from DI stage
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DI_bra => DI_bra, -- Branch instruction
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DI_bra => DI_bra, -- Branch instruction
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DI_link => DI_link, -- Branch with link
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DI_link => DI_link, -- Branch with link
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DI_op1 => DI_op1, -- Operand 1 for alu
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DI_op1 => DI_op1, -- Operand 1 for alu
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DI_op2 => DI_op2, -- Operand 2 for alu
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DI_op2 => DI_op2, -- Operand 2 for alu
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DI_code_ual => DI_code_ual, -- Alu operation
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DI_code_ual => DI_code_ual, -- Alu operation
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DI_offset => DI_offset, -- Offset for address calculation
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DI_offset => DI_offset, -- Offset for address calculation
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DI_adr_reg_dest => DI_adr_reg_dest, -- Destination register address for the result
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DI_adr_reg_dest => DI_adr_reg_dest, -- Destination register address for the result
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DI_ecr_reg => DI_ecr_reg, -- Effective writing of the result
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DI_ecr_reg => DI_ecr_reg, -- Effective writing of the result
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DI_mode => DI_mode, -- Address mode (relative to pc ou index by a register)
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DI_mode => DI_mode, -- Address mode (relative to pc ou index by a register)
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DI_op_mem => DI_op_mem, -- Memory operation
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DI_op_mem => DI_op_mem, -- Memory operation
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DI_r_w => DI_r_w, -- Type of memory operation (read or write)
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DI_r_w => DI_r_w, -- Type of memory operation (read or write)
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DI_adr => DI_adr, -- Instruction address
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DI_adr => DI_adr, -- Instruction address
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DI_exc_cause => DI_exc_cause, -- Potential cause exception
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DI_exc_cause => DI_exc_cause, -- Potential cause exception
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DI_level => DI_level, -- Availability stage of the result for bypassing
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DI_level => DI_level, -- Availability stage of the result for bypassing
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DI_it_ok => DI_it_ok, -- Allow hardware interruptions
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DI_it_ok => DI_it_ok, -- Allow hardware interruptions
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EX2_data_hilo => ex2_data_hilo, -- entrada p resultado do hilo p2
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EX2_data_hilo => ex2_data_hilo, -- entrada p resultado do hilo p2
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EX_data_hilo => ex_data_hilo, -- saida p resultado do hilo p1
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EX_data_hilo => ex_data_hilo, -- saida p resultado do hilo p1
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-- Synchronous outputs to MEM stage
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-- Synchronous outputs to MEM stage
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EX_adr => EX_adr, -- Instruction address
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EX_adr => EX_adr, -- Instruction address
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EX_bra_confirm => EX_bra_confirm, -- Branch execution confirmation
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EX_bra_confirm => EX_bra_confirm, -- Branch execution confirmation
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EX_data_ual => EX_data_ual, -- Ual result
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EX_data_ual => EX_data_ual, -- Ual result
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EX_adresse => EX_adresse, -- Address calculation result
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EX_adresse => EX_adresse, -- Address calculation result
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EX_adresse_p1p2 => ex_adresse_p1p2_s, --resultado do calculo do endereco do desvio + 4 para pipe 2. 12-08-2018
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EX_adresse_p1p2 => ex_adresse_p1p2_s, --resultado do calculo do endereco do desvio + 4 para pipe 2. 12-08-2018
|
EX_adr_reg_dest => EX_adr_reg_dest, -- Destination register for the result
|
EX_adr_reg_dest => EX_adr_reg_dest, -- Destination register for the result
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EX_ecr_reg => EX_ecr_reg, -- Effective writing of the result
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EX_ecr_reg => EX_ecr_reg, -- Effective writing of the result
|
EX_op_mem => EX_op_mem, -- Memory operation needed
|
EX_op_mem => EX_op_mem, -- Memory operation needed
|
EX_r_w => EX_r_w, -- Type of memory operation (read or write)
|
EX_r_w => EX_r_w, -- Type of memory operation (read or write)
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EX_exc_cause => EX_exc_cause, -- Potential cause exception
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EX_exc_cause => EX_exc_cause, -- Potential cause exception
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EX_level => EX_level, -- Availability stage of result for bypassing
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EX_level => EX_level, -- Availability stage of result for bypassing
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EX_it_ok => EX_it_ok -- Allow hardware interruptions
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EX_it_ok => EX_it_ok -- Allow hardware interruptions
|
);
|
);
|
|
|
|
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U5_mem : pps_mem port map (
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U5_mem : pps_mem port map (
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clock => clock,
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clock => clock,
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clock2 => clock2,
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clock2 => clock2,
|
reset => reset,
|
reset => reset,
|
stop_all => stop_all, -- Unconditionnal locking of the outputs
|
stop_all => stop_all, -- Unconditionnal locking of the outputs
|
stop_all2 => stop_all2,
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stop_all2 => stop_all2,
|
|
|
clear => interrupt, -- Clear the pipeline stage
|
clear => interrupt, -- Clear the pipeline stage
|
|
|
-- Interface with the control bus
|
-- Interface with the control bus
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MTC_data => MTC_data, -- Data to write in memory
|
MTC_data => MTC_data, -- Data to write in memory
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MTC_adr => MTC_adr, -- Address for memory
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MTC_adr => MTC_adr, -- Address for memory
|
MTC_r_w => MTC_r_w, -- Read/Write in memory
|
MTC_r_w => MTC_r_w, -- Read/Write in memory
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MTC_req => MTC_req, -- Request access to memory
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MTC_req => MTC_req, -- Request access to memory
|
CTM_data => CTM_data, -- Data from memory
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CTM_data => CTM_data, -- Data from memory
|
|
|
-- Datas from Execution stage
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-- Datas from Execution stage
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EX_adr => EX_adr, -- Instruction address
|
EX_adr => EX_adr, -- Instruction address
|
EX_data_ual => EX_data_ual, -- Result of alu operation
|
EX_data_ual => EX_data_ual, -- Result of alu operation
|
EX_adresse => EX_adresse, -- Result of the calculation of the address
|
EX_adresse => EX_adresse, -- Result of the calculation of the address
|
EX_adresse_p1p2 => ex_adresse_p1p2_s, --resultado do calculo do endereco do desvio + 4 para pipe 2. 12-08-2018
|
EX_adresse_p1p2 => ex_adresse_p1p2_s, --resultado do calculo do endereco do desvio + 4 para pipe 2. 12-08-2018
|
EX_bra_confirm => EX_bra_confirm, -- Confirmacao do branch no pipe 1 (26-07-18)
|
EX_bra_confirm => EX_bra_confirm, -- Confirmacao do branch no pipe 1 (26-07-18)
|
EX_adr_reg_dest => EX_adr_reg_dest, -- Destination register address for the result
|
EX_adr_reg_dest => EX_adr_reg_dest, -- Destination register address for the result
|
EX_ecr_reg => EX_ecr_reg, -- Effective writing of the result
|
EX_ecr_reg => EX_ecr_reg, -- Effective writing of the result
|
EX_op_mem => EX_op_mem, -- Memory operation needed
|
EX_op_mem => EX_op_mem, -- Memory operation needed
|
EX_r_w => EX_r_w, -- Type of memory operation (read or write)
|
EX_r_w => EX_r_w, -- Type of memory operation (read or write)
|
EX_exc_cause => EX_exc_cause, -- Potential exception cause
|
EX_exc_cause => EX_exc_cause, -- Potential exception cause
|
EX_level => EX_level, -- Availability stage for the result for bypassing
|
EX_level => EX_level, -- Availability stage for the result for bypassing
|
EX_it_ok => EX_it_ok, -- Allow hardware interruptions
|
EX_it_ok => EX_it_ok, -- Allow hardware interruptions
|
|
|
-- Synchronous outputs for bypass unit
|
-- Synchronous outputs for bypass unit
|
MEM_adr => MEM_adr, -- Instruction address
|
MEM_adr => MEM_adr, -- Instruction address
|
MEM_adr_reg_dest=>MEM_adr_reg_dest, -- Destination register address
|
MEM_adr_reg_dest=>MEM_adr_reg_dest, -- Destination register address
|
MEM_ecr_reg => MEM_ecr_reg, -- Writing of the destination register
|
MEM_ecr_reg => MEM_ecr_reg, -- Writing of the destination register
|
MEM_data_ecr => MEM_data_ecr, -- Data to write (from alu or memory)
|
MEM_data_ecr => MEM_data_ecr, -- Data to write (from alu or memory)
|
MEM_exc_cause => MEM_exc_cause, -- Potential exception cause
|
MEM_exc_cause => MEM_exc_cause, -- Potential exception cause
|
MEM_level => MEM_level, -- Availability stage for the result for bypassing
|
MEM_level => MEM_level, -- Availability stage for the result for bypassing
|
MEM_it_ok => MEM_it_ok, -- Allow hardware interruptions
|
MEM_it_ok => MEM_it_ok, -- Allow hardware interruptions
|
-- duplicacao
|
-- duplicacao
|
-- Interface with the control bus
|
-- Interface with the control bus
|
MTC_data2 => MTC_data2, -- Data to write in memory
|
MTC_data2 => MTC_data2, -- Data to write in memory
|
MTC_adr2 => MTC_adr2, -- Address for memory
|
MTC_adr2 => MTC_adr2, -- Address for memory
|
MTC_r_w2 => MTC_r_w2, -- Read/Write in memory
|
MTC_r_w2 => MTC_r_w2, -- Read/Write in memory
|
MTC_req2 => MTC_req2, -- Request access to memory
|
MTC_req2 => MTC_req2, -- Request access to memory
|
CTM_data2 => CTM_data2, -- Data from memory
|
CTM_data2 => CTM_data2, -- Data from memory
|
|
|
-- Datas from Execution 2 stage
|
-- Datas from Execution 2 stage
|
EX_adr2 => EX_adr2, -- Instruction address
|
EX_adr2 => EX_adr2, -- Instruction address
|
EX_data_ual2 => EX_data_ual2, -- Result of alu operation
|
EX_data_ual2 => EX_data_ual2, -- Result of alu operation
|
EX_adresse2 => EX_adresse2, -- Result of the calculation of the address
|
EX_adresse2 => EX_adresse2, -- Result of the calculation of the address
|
EX_adresse_p2p1 => ex_adresse_p2p1_s, --resultado do calculo do endereco do desvio + 4 para pipe 1. 12-08-2018
|
EX_adresse_p2p1 => ex_adresse_p2p1_s, --resultado do calculo do endereco do desvio + 4 para pipe 1. 12-08-2018
|
EX_bra_confirm2 => EX_bra_confirm2, -- Confirmacao do branch no pipe 2 (26-07-18)
|
EX_bra_confirm2 => EX_bra_confirm2, -- Confirmacao do branch no pipe 2 (26-07-18)
|
EX_adr_reg_dest2 => EX_adr_reg_dest2, -- Destination register address for the result
|
EX_adr_reg_dest2 => EX_adr_reg_dest2, -- Destination register address for the result
|
EX_ecr_reg2 => EX_ecr_reg2, -- Effective writing of the result
|
EX_ecr_reg2 => EX_ecr_reg2, -- Effective writing of the result
|
EX_op_mem2 => EX_op_mem2, -- Memory operation needed
|
EX_op_mem2 => EX_op_mem2, -- Memory operation needed
|
EX_r_w2 => EX_r_w2, -- Type of memory operation (read or write)
|
EX_r_w2 => EX_r_w2, -- Type of memory operation (read or write)
|
EX_exc_cause2 => EX_exc_cause2, -- Potential exception cause
|
EX_exc_cause2 => EX_exc_cause2, -- Potential exception cause
|
EX_level2 => EX_level2, -- Availability stage for the result for bypassing
|
EX_level2 => EX_level2, -- Availability stage for the result for bypassing
|
EX_it_ok2 => EX_it_ok2, -- Allow hardware interruptions
|
EX_it_ok2 => EX_it_ok2, -- Allow hardware interruptions
|
|
|
-- Synchronous outputs for bypass unit
|
-- Synchronous outputs for bypass unit
|
MEM_adr2 => MEM_adr2, -- Instruction address
|
MEM_adr2 => MEM_adr2, -- Instruction address
|
MEM_adr_reg_dest2=>MEM_adr_reg_dest2, -- Destination register address
|
MEM_adr_reg_dest2=>MEM_adr_reg_dest2, -- Destination register address
|
MEM_ecr_reg2 => MEM_ecr_reg2, -- Writing of the destination register
|
MEM_ecr_reg2 => MEM_ecr_reg2, -- Writing of the destination register
|
MEM_data_ecr2 => MEM_data_ecr2, -- Data to write (from alu or memory)
|
MEM_data_ecr2 => MEM_data_ecr2, -- Data to write (from alu or memory)
|
MEM_exc_cause2 => MEM_exc_cause2, -- Potential exception cause
|
MEM_exc_cause2 => MEM_exc_cause2, -- Potential exception cause
|
MEM_level2 => MEM_level2, -- Availability stage for the result for bypassing
|
MEM_level2 => MEM_level2, -- Availability stage for the result for bypassing
|
MEM_it_ok2 => MEM_it_ok2 -- Allow hardware interruptions
|
MEM_it_ok2 => MEM_it_ok2 -- Allow hardware interruptions
|
);
|
);
|
|
|
|
|
U6_renvoi : renvoi port map (
|
U6_renvoi : renvoi port map (
|
-- Register access signals
|
-- Register access signals
|
adr1 => adr_reg1, -- Operand 1 address
|
adr1 => adr_reg1, -- Operand 1 address
|
adr2 => adr_reg2, -- Operand 2 address
|
adr2 => adr_reg2, -- Operand 2 address
|
use1 => use1, -- Operand 1 utilisation
|
use1 => use1, -- Operand 1 utilisation
|
use2 => use2, -- Operand 2 utilisation
|
use2 => use2, -- Operand 2 utilisation
|
|
|
data1 => data1, -- First register value
|
data1 => data1, -- First register value
|
data2 => data2, -- Second register value
|
data2 => data2, -- Second register value
|
alea => alea, -- Unresolved hazards detected
|
alea => alea, -- Unresolved hazards detected
|
|
|
-- Bypass signals of the intermediary datas
|
-- Bypass signals of the intermediary datas
|
DI_level => DI_level, -- Availability level of the data
|
DI_level => DI_level, -- Availability level of the data
|
DI_adr => DI_adr_reg_dest, -- Register destination of the result
|
DI_adr => DI_adr_reg_dest, -- Register destination of the result
|
DI_ecr => DI_ecr_reg, -- Writing register request
|
DI_ecr => DI_ecr_reg, -- Writing register request
|
DI_data => DI_op2, -- Data to used
|
DI_data => DI_op2, -- Data to used
|
|
|
EX_level => EX_level, -- Availability level of the data
|
EX_level => EX_level, -- Availability level of the data
|
EX_adr => EX_adr_reg_dest, -- Register destination of the result
|
EX_adr => EX_adr_reg_dest, -- Register destination of the result
|
EX_ecr => EX_ecr_reg, -- Writing register request
|
EX_ecr => EX_ecr_reg, -- Writing register request
|
EX_data => EX_data_ual, -- Data to used
|
EX_data => EX_data_ual, -- Data to used
|
|
|
MEM_level => MEM_level, -- Availability level of the data
|
MEM_level => MEM_level, -- Availability level of the data
|
MEM_adr => MEM_adr_reg_dest, -- Register destination of the result
|
MEM_adr => MEM_adr_reg_dest, -- Register destination of the result
|
MEM_ecr => MEM_ecr_reg, -- Writing register request
|
MEM_ecr => MEM_ecr_reg, -- Writing register request
|
MEM_data => MEM_data_ecr, -- Data to used
|
MEM_data => MEM_data_ecr, -- Data to used
|
|
|
interrupt => interrupt, -- Exceptions or interruptions
|
interrupt => interrupt, -- Exceptions or interruptions
|
|
|
-- Connexion to the differents bank of register
|
-- Connexion to the differents bank of register
|
|
|
-- Writing commands for writing in the registers
|
-- Writing commands for writing in the registers
|
write_data => write_data, -- Data to write
|
write_data => write_data, -- Data to write
|
write_adr => write_adr, -- Address of the register to write
|
write_adr => write_adr, -- Address of the register to write
|
write_GPR => write_GPR, -- Selection in the internal registers
|
write_GPR => write_GPR, -- Selection in the internal registers
|
write_SCP => write_SCP, -- Selection in the coprocessor system registers
|
write_SCP => write_SCP, -- Selection in the coprocessor system registers
|
|
|
-- Reading commands for Reading in the registers
|
-- Reading commands for Reading in the registers
|
read_adr1 => read_adr1, -- Address of the first register to read
|
read_adr1 => read_adr1, -- Address of the first register to read
|
read_adr2 => read_adr2, -- Address of the second register to read
|
read_adr2 => read_adr2, -- Address of the second register to read
|
read_data1_GPR => read_data1_GPR, -- Value of operand 1 from the internal registers
|
read_data1_GPR => read_data1_GPR, -- Value of operand 1 from the internal registers
|
read_data1_SCP => read_data1_SCP, -- Value of operand 2 from the internal registers
|
read_data1_SCP => read_data1_SCP, -- Value of operand 2 from the internal registers
|
read_data2_GPR => read_data2_GPR, -- Value of operand 1 from the coprocessor system registers
|
read_data2_GPR => read_data2_GPR, -- Value of operand 1 from the coprocessor system registers
|
read_data2_SCP => read_data2_SCP, -- Value of operand 2 from the coprocessor system registers
|
read_data2_SCP => read_data2_SCP, -- Value of operand 2 from the coprocessor system registers
|
-- duplicacao
|
-- duplicacao
|
-- Register access signals
|
-- Register access signals
|
adr3 => adr_reg3, -- Operand 1 address
|
adr3 => adr_reg3, -- Operand 1 address
|
adr4 => adr_reg4, -- Operand 2 address
|
adr4 => adr_reg4, -- Operand 2 address
|
use12 => use3, -- Operand 1 utilisation
|
use12 => use3, -- Operand 1 utilisation
|
use22 => use4, -- Operand 2 utilisation
|
use22 => use4, -- Operand 2 utilisation
|
|
|
data3 => data3, -- First register value
|
data3 => data3, -- First register value
|
data4 => data4, -- Second register value
|
data4 => data4, -- Second register value
|
alea2 => alea2, -- Unresolved hazards detected
|
alea2 => alea2, -- Unresolved hazards detected
|
|
|
-- Bypass signals of the intermediary datas
|
-- Bypass signals of the intermediary datas
|
DI_level2 => DI_level2, -- Availability level of the data
|
DI_level2 => DI_level2, -- Availability level of the data
|
DI_adr2 => DI_adr_reg_dest2, -- Register destination of the result
|
DI_adr2 => DI_adr_reg_dest2, -- Register destination of the result
|
DI_ecr2 => DI_ecr_reg2, -- Writing register request
|
DI_ecr2 => DI_ecr_reg2, -- Writing register request
|
DI_data2 => DI_op4, -- Data to used
|
DI_data2 => DI_op4, -- Data to used
|
|
|
EX_level2 => EX_level2, -- Availability level of the data
|
EX_level2 => EX_level2, -- Availability level of the data
|
EX_adr2 => EX_adr_reg_dest2, -- Register destination of the result
|
EX_adr2 => EX_adr_reg_dest2, -- Register destination of the result
|
EX_ecr2 => EX_ecr_reg2, -- Writing register request
|
EX_ecr2 => EX_ecr_reg2, -- Writing register request
|
EX_data2 => EX_data_ual2, -- Data to used
|
EX_data2 => EX_data_ual2, -- Data to used
|
|
|
MEM_level2 => MEM_level2, -- Availability level of the data
|
MEM_level2 => MEM_level2, -- Availability level of the data
|
MEM_adr2 => MEM_adr_reg_dest2, -- Register destination of the result
|
MEM_adr2 => MEM_adr_reg_dest2, -- Register destination of the result
|
MEM_ecr2 => MEM_ecr_reg2, -- Writing register request
|
MEM_ecr2 => MEM_ecr_reg2, -- Writing register request
|
MEM_data2 => MEM_data_ecr2, -- Data to used
|
MEM_data2 => MEM_data_ecr2, -- Data to used
|
|
|
-- Connexion to the differents bank of register
|
-- Connexion to the differents bank of register
|
|
|
-- Writing commands for writing in the registers
|
-- Writing commands for writing in the registers
|
write_data2 => write_data2, -- Data to write
|
write_data2 => write_data2, -- Data to write
|
write_adr2 => write_adr2, -- Address of the register to write
|
write_adr2 => write_adr2, -- Address of the register to write
|
write_GPR2 => write_GPR2, -- Selection in the internal registers
|
write_GPR2 => write_GPR2, -- Selection in the internal registers
|
--write_SCP2 => write_SCP, -- Selection in the coprocessor system registers
|
--write_SCP2 => write_SCP, -- Selection in the coprocessor system registers
|
|
|
-- Reading commands for Reading in the registers
|
-- Reading commands for Reading in the registers
|
read_adr3 => read_adr3, -- Address of the first register to read
|
read_adr3 => read_adr3, -- Address of the first register to read
|
read_adr4 => read_adr4, -- Address of the second register to read
|
read_adr4 => read_adr4, -- Address of the second register to read
|
read_data3_GPR => read_data3_GPR, -- Value of operand 1 from the internal registers
|
read_data3_GPR => read_data3_GPR, -- Value of operand 1 from the internal registers
|
read_data3_SCP => read_data3_SCP, -- Value of operand 2 from the internal registers
|
read_data3_SCP => read_data3_SCP, -- Value of operand 2 from the internal registers
|
read_data4_GPR => read_data4_GPR, -- Value of operand 1 from the coprocessor system registers
|
read_data4_GPR => read_data4_GPR, -- Value of operand 1 from the coprocessor system registers
|
read_data4_SCP => read_data4_SCP -- Value of operand 2 from the coprocessor system registers
|
read_data4_SCP => read_data4_SCP -- Value of operand 2 from the coprocessor system registers
|
);
|
);
|
|
|
|
|
U7_banc : banc port map(
|
U7_banc : banc port map(
|
clock => clock,
|
clock => clock,
|
clock2 => clock2,
|
clock2 => clock2,
|
reset => reset,
|
reset => reset,
|
|
|
-- Register addresses to read
|
-- Register addresses to read
|
reg_src1 => read_adr1,
|
reg_src1 => read_adr1,
|
reg_src2 => read_adr2,
|
reg_src2 => read_adr2,
|
|
|
-- Register address to write and its data
|
-- Register address to write and its data
|
reg_dest => write_adr,
|
reg_dest => write_adr,
|
donnee => write_data,
|
donnee => write_data,
|
|
|
-- Write signal
|
-- Write signal
|
cmd_ecr => write_GPR,
|
cmd_ecr => write_GPR,
|
|
|
-- Bank outputs
|
-- Bank outputs
|
data_src1 => read_data1_GPR,
|
data_src1 => read_data1_GPR,
|
data_src2 => read_data2_GPR,
|
data_src2 => read_data2_GPR,
|
|
|
-- Register addresses to read
|
-- Register addresses to read
|
reg_src3 => read_adr3,
|
reg_src3 => read_adr3,
|
reg_src4 => read_adr4,
|
reg_src4 => read_adr4,
|
|
|
-- Register address to write and its data
|
-- Register address to write and its data
|
reg_dest2 => write_adr2,
|
reg_dest2 => write_adr2,
|
donnee2 => write_data2,
|
donnee2 => write_data2,
|
|
|
-- Write signal
|
-- Write signal
|
cmd_ecr2 => write_GPR2,
|
cmd_ecr2 => write_GPR2,
|
|
|
-- Bank outputs
|
-- Bank outputs
|
data_src3 => read_data3_GPR,
|
data_src3 => read_data3_GPR,
|
data_src4 => read_data4_GPR
|
data_src4 => read_data4_GPR
|
);
|
);
|
|
|
|
|
U8_syscop : syscop port map (
|
U8_syscop : syscop port map (
|
clock => clock,
|
clock => clock,
|
reset => reset,
|
reset => reset,
|
|
|
-- Datas from the pipeline
|
-- Datas from the pipeline
|
MEM_adr => MEM_adr, -- Address (PC) of the current instruction in the pipeline end -> responsible of the exception
|
MEM_adr => MEM_adr, -- Address (PC) of the current instruction in the pipeline end -> responsible of the exception
|
MEM_exc_cause => MEM_exc_cause, -- Potential cause exception of that instruction
|
MEM_exc_cause => MEM_exc_cause, -- Potential cause exception of that instruction
|
MEM_it_ok => MEM_it_ok, -- Allow hardware interruptions
|
MEM_it_ok => MEM_it_ok, -- Allow hardware interruptions
|
|
|
-- Hardware interruption
|
-- Hardware interruption
|
it_mat => it_mat_clk, -- Hardware interruption detected
|
it_mat => it_mat_clk, -- Hardware interruption detected
|
|
|
-- Interruption controls
|
-- Interruption controls
|
interrupt => interrupt, -- Interruption to take into account
|
interrupt => interrupt, -- Interruption to take into account
|
vecteur_it => vecteur_it, -- Interruption vector
|
vecteur_it => vecteur_it, -- Interruption vector
|
|
|
-- Writing request in register bank
|
-- Writing request in register bank
|
write_data => write_data, -- Data to write
|
write_data => write_data, -- Data to write
|
write_adr => write_adr, -- Address of the register to write
|
write_adr => write_adr, -- Address of the register to write
|
write_SCP => write_SCP, -- Writing request
|
write_SCP => write_SCP, -- Writing request
|
|
|
-- Reading request in register bank
|
-- Reading request in register bank
|
read_adr1 => read_adr1, -- Address of the first register
|
read_adr1 => read_adr1, -- Address of the first register
|
read_adr2 => read_adr2, -- Address of the second register
|
read_adr2 => read_adr2, -- Address of the second register
|
read_data1 => read_data1_SCP, -- Value of register 1
|
read_data1 => read_data1_SCP, -- Value of register 1
|
read_data2 => read_data2_SCP, -- Value of register 2
|
read_data2 => read_data2_SCP, -- Value of register 2
|
--mod
|
--mod
|
MEM_adr2 => MEM_adr2,
|
MEM_adr2 => MEM_adr2,
|
MEM_exc_cause2 => MEM_exc_cause2,
|
MEM_exc_cause2 => MEM_exc_cause2,
|
MEM_it_ok2 => MEM_it_ok2,
|
MEM_it_ok2 => MEM_it_ok2,
|
|
|
write_data2 => write_data2,
|
write_data2 => write_data2,
|
write_adr2 => write_adr2,
|
write_adr2 => write_adr2,
|
write_SCP2 => zero,
|
write_SCP2 => zero,
|
|
|
read_adr3 => read_adr3,
|
read_adr3 => read_adr3,
|
read_adr4 => read_adr4,
|
read_adr4 => read_adr4,
|
read_data3 => read_data3_SCP,
|
read_data3 => read_data3_SCP,
|
read_data4 => read_data4_SCP
|
read_data4 => read_data4_SCP
|
);
|
);
|
|
|
|
|
U9_bus_ctrl01 : bus_ctrl01 port map (
|
U9_bus_ctrl01 : bus_ctrl01 port map (
|
clock => clock,
|
clock => clock,
|
reset => reset,
|
reset => reset,
|
|
|
-- Interruption in the pipeline
|
-- Interruption in the pipeline
|
interrupt => interrupt,
|
interrupt => interrupt,
|
|
|
-- Interface for the Instruction Extraction Stage
|
-- Interface for the Instruction Extraction Stage
|
adr_from_ei => ETC_adr, -- The address of the data to read
|
adr_from_ei => ETC_adr, -- The address of the data to read
|
instr_to_ei => CTE_instr, -- Instruction from the memory
|
instr_to_ei => CTE_instr, -- Instruction from the memory
|
-- Interface with the MEMory Stage
|
-- Interface with the MEMory Stage
|
req_from_mem => MTC_req, -- Request to access the ram
|
req_from_mem => MTC_req, -- Request to access the ram
|
r_w_from_mem => MTC_r_w, -- Read/Write request
|
r_w_from_mem => MTC_r_w, -- Read/Write request
|
adr_from_mem => MTC_adr, -- Address in ram
|
adr_from_mem => MTC_adr, -- Address in ram
|
data_from_mem => MTC_data, -- Data to write in ram
|
data_from_mem => MTC_data, -- Data to write in ram
|
data_to_mem => CTM_data, -- Data from the ram to the MEMory stage
|
data_to_mem => CTM_data, -- Data from the ram to the MEMory stage
|
|
|
-- RAM interface signals
|
-- RAM interface signals
|
req_to_ram => ram_req, -- Request to ram
|
req_to_ram => ram_req, -- Request to ram
|
adr_to_ram => ram_adr, -- Address of the data to read or write
|
adr_to_ram => ram_adr, -- Address of the data to read or write
|
r_w_to_ram => ram_r_w, -- Read/Write request
|
r_w_to_ram => ram_r_w, -- Read/Write request
|
ack_from_ram => ram_ack, -- Acknowledge from the memory
|
ack_from_ram => ram_ack, -- Acknowledge from the memory
|
data_inout_ram => ram_data, -- Data from/to the memory
|
data_inout_ram => ram_data, -- Data from/to the memory
|
|
|
-- Pipeline progress control signal
|
-- Pipeline progress control signal
|
stop_all => stop_all
|
stop_all => stop_all
|
);
|
);
|
|
|
|
|
U10_ei_2 : pps_ei_2 port map (
|
U10_ei_2 : pps_ei_2 port map (
|
clock => clock2,
|
clock => clock2,
|
reset => reset,
|
reset => reset,
|
clear => interrupt, -- Clear the pipeline stage
|
clear => interrupt, -- Clear the pipeline stage
|
stop_all2 => stop_all2, -- Evolution locking signal
|
stop_all2 => stop_all2, -- Evolution locking signal
|
|
|
-- Asynchronous inputs
|
-- Asynchronous inputs
|
stop_ei => alea2EI2, -- Lock the EI_adr and Ei_instr registers
|
stop_ei => alea2EI2, -- Lock the EI_adr and Ei_instr registers
|
genop => genop2, -- Send nops
|
genop => genop2, -- Send nops
|
|
|
-- interface Controler - EI
|
-- interface Controler - EI
|
CTE_instr => CTE_instr2, -- Instruction from the memory
|
CTE_instr => CTE_instr2, -- Instruction from the memory
|
ETC_adr => ETC_adr2, -- Address to read in memory (ja feito pelo EI)
|
ETC_adr => ETC_adr2, -- Address to read in memory (ja feito pelo EI)
|
|
|
-- Synchronous inputs from PF stage
|
-- Synchronous inputs from PF stage
|
PF_pc => PF_pc_4, -- Current value of the pc + 4
|
PF_pc => PF_pc_4, -- Current value of the pc + 4
|
|
|
-- Synchronous outputs to DI stage
|
-- Synchronous outputs to DI stage
|
EI_instr => EI_instr2, -- Read interface
|
EI_instr => EI_instr2, -- Read interface
|
EI_adr => EI_adr2, -- Address from the read instruction
|
EI_adr => EI_adr2, -- Address from the read instruction
|
EI_it_ok => EI_it_ok2 -- Allow hardware interruptions
|
EI_it_ok => EI_it_ok2 -- Allow hardware interruptions
|
);
|
);
|
|
|
|
|
U11_di2 : pps_di_2 port map (
|
U11_di2 : pps_di_2 port map (
|
clock => clock2,
|
clock => clock2,
|
reset => reset,
|
reset => reset,
|
stop_all2 => stop_all2, -- Unconditionnal locking of the outputs
|
stop_all2 => stop_all2, -- Unconditionnal locking of the outputs
|
clear => interrupt, -- Clear the pipeline stage (nop in the outputs)
|
clear => interrupt, -- Clear the pipeline stage (nop in the outputs)
|
|
|
-- Asynchronous outputs
|
-- Asynchronous outputs
|
bra_detect => bra_detect2, -- Branch detection in the current instruction
|
bra_detect => bra_detect2, -- Branch detection in the current instruction
|
|
|
-- Asynchronous connexion with the register management and data bypass unit
|
-- Asynchronous connexion with the register management and data bypass unit
|
adr_reg1 => adr_reg3, -- Address of the first register operand
|
adr_reg1 => adr_reg3, -- Address of the first register operand
|
adr_reg2 => adr_reg4, -- Address of the second register operand
|
adr_reg2 => adr_reg4, -- Address of the second register operand
|
use1 => use3, -- Effective use of operand 1
|
use1 => use3, -- Effective use of operand 1
|
use2 => use4, -- Effective use of operand 2
|
use2 => use4, -- Effective use of operand 2
|
--iload2 => iload2,
|
--iload2 => iload2,
|
istore2 => istore2,
|
istore2 => istore2,
|
stop_di => alea2DI2, -- Unresolved detected : send nop in the pipeline
|
stop_di => alea2DI2, -- Unresolved detected : send nop in the pipeline
|
data1 => data3, -- Operand register 1
|
data1 => data3, -- Operand register 1
|
data2 => data4, -- Operand register 2
|
data2 => data4, -- Operand register 2
|
|
|
-- Datas from EI stage
|
-- Datas from EI stage
|
EI_adr => EI_adr2, -- Address of the instruction
|
EI_adr => EI_adr2, -- Address of the instruction
|
EI_instr => EI_instr2, -- The instruction to decode
|
EI_instr => EI_instr2, -- The instruction to decode
|
EI_it_ok => EI_it_ok2, -- Allow hardware interruptions
|
EI_it_ok => EI_it_ok2, -- Allow hardware interruptions
|
|
|
-- Synchronous output to EX2 stage
|
-- Synchronous output to EX2 stage
|
DI_bra => DI_bra2, -- Branch decoded
|
DI_bra => DI_bra2, -- Branch decoded
|
DI_link => DI_link2, -- A link for that instruction
|
DI_link => DI_link2, -- A link for that instruction
|
DI_op1 => DI_op3, -- operand 1 for alu
|
DI_op1 => DI_op3, -- operand 1 for alu
|
DI_op2 => DI_op4, -- operand 2 for alu
|
DI_op2 => DI_op4, -- operand 2 for alu
|
DI_code_ual => DI_code_ual2, -- Alu operation
|
DI_code_ual => DI_code_ual2, -- Alu operation
|
DI_offset => DI_offset2, -- Offset for the address calculation
|
DI_offset => DI_offset2, -- Offset for the address calculation
|
DI_adr_reg_dest => DI_adr_reg_dest2, -- Address of the destination register of the result
|
DI_adr_reg_dest => DI_adr_reg_dest2, -- Address of the destination register of the result
|
DI_ecr_reg => DI_ecr_reg2, -- Effective writing of the result
|
DI_ecr_reg => DI_ecr_reg2, -- Effective writing of the result
|
DI_mode => DI_mode2, -- Address mode (relative to pc or indexed to a register)
|
DI_mode => DI_mode2, -- Address mode (relative to pc or indexed to a register)
|
DI_op_mem => DI_op_mem2, -- Memory operation request
|
DI_op_mem => DI_op_mem2, -- Memory operation request
|
DI_r_w => DI_r_w2, -- Type of memory operation (reading or writing)
|
DI_r_w => DI_r_w2, -- Type of memory operation (reading or writing)
|
DI_adr => DI_adr2, -- Address of the decoded instruction
|
DI_adr => DI_adr2, -- Address of the decoded instruction
|
DI_exc_cause => DI_exc_cause2, -- Potential exception detected
|
DI_exc_cause => DI_exc_cause2, -- Potential exception detected
|
DI_level => DI_level2, -- Availability of the result for the data bypass
|
DI_level => DI_level2, -- Availability of the result for the data bypass
|
DI_it_ok => DI_it_ok2 -- Allow hardware interruptions
|
DI_it_ok => DI_it_ok2 -- Allow hardware interruptions
|
);
|
);
|
|
|
|
|
U12_ex2 : pps_ex_2 port map (
|
U12_ex2 : pps_ex_2 port map (
|
clock => clock,
|
clock => clock,
|
clock2 => clock2,
|
clock2 => clock2,
|
reset => reset,
|
reset => reset,
|
stop_all => stop_all,
|
stop_all => stop_all,
|
stop_all2 => stop_all2, -- Unconditionnal locking of outputs
|
stop_all2 => stop_all2, -- Unconditionnal locking of outputs
|
clear => interrupt, -- Clear the pipeline stage
|
clear => interrupt, -- Clear the pipeline stage
|
|
|
-- Datas from DI2 stage
|
-- Datas from DI2 stage
|
DI_bra => DI_bra2, -- Branch instruction
|
DI_bra => DI_bra2, -- Branch instruction
|
DI_link => DI_link2, -- Branch with link
|
DI_link => DI_link2, -- Branch with link
|
DI_op1 => DI_op3, -- Operand 1 for alu
|
DI_op1 => DI_op3, -- Operand 1 for alu
|
DI_op2 => DI_op4, -- Operand 2 for alu
|
DI_op2 => DI_op4, -- Operand 2 for alu
|
DI_code_ual => DI_code_ual2, -- Alu operation
|
DI_code_ual => DI_code_ual2, -- Alu operation
|
DI_offset => DI_offset2, -- Offset for address calculation
|
DI_offset => DI_offset2, -- Offset for address calculation
|
DI_adr_reg_dest => DI_adr_reg_dest2, -- Destination register address for the result
|
DI_adr_reg_dest => DI_adr_reg_dest2, -- Destination register address for the result
|
DI_ecr_reg => DI_ecr_reg2, -- Effective writing of the result
|
DI_ecr_reg => DI_ecr_reg2, -- Effective writing of the result
|
DI_mode => DI_mode2, -- Address mode (relative to pc ou index by a register)
|
DI_mode => DI_mode2, -- Address mode (relative to pc ou index by a register)
|
DI_op_mem => DI_op_mem2, -- Memory operation
|
DI_op_mem => DI_op_mem2, -- Memory operation
|
DI_r_w => DI_r_w2, -- Type of memory operation (read or write)
|
DI_r_w => DI_r_w2, -- Type of memory operation (read or write)
|
DI_adr => DI_adr2, -- Instruction address
|
DI_adr => DI_adr2, -- Instruction address
|
DI_exc_cause => DI_exc_cause2, -- Potential cause exception
|
DI_exc_cause => DI_exc_cause2, -- Potential cause exception
|
DI_level => DI_level2, -- Availability stage of the result for bypassing
|
DI_level => DI_level2, -- Availability stage of the result for bypassing
|
DI_it_ok => DI_it_ok2, -- Allow hardware interruptions
|
DI_it_ok => DI_it_ok2, -- Allow hardware interruptions
|
EX2_data_hilo => ex2_data_hilo, -- saida p resultado do hilo p2
|
EX2_data_hilo => ex2_data_hilo, -- saida p resultado do hilo p2
|
EX_data_hilo => ex_data_hilo, -- entrada p resultado do hilo p1
|
EX_data_hilo => ex_data_hilo, -- entrada p resultado do hilo p1
|
-- Synchronous outputs to MEM stage
|
-- Synchronous outputs to MEM stage
|
EX_adr => EX_adr2, -- Instruction address
|
EX_adr => EX_adr2, -- Instruction address
|
EX_bra_confirm => EX_bra_confirm2, -- Branch execution confirmation
|
EX_bra_confirm => EX_bra_confirm2, -- Branch execution confirmation
|
EX_data_ual => EX_data_ual2, -- Ual result
|
EX_data_ual => EX_data_ual2, -- Ual result
|
EX_adresse => EX_adresse2, -- Address calculation result
|
EX_adresse => EX_adresse2, -- Address calculation result
|
EX_adresse_p2p1 => ex_adresse_p2p1_s, --resultado do calculo do endereco do desvio + 4 para pipe 1. 12-08-2018
|
EX_adresse_p2p1 => ex_adresse_p2p1_s, --resultado do calculo do endereco do desvio + 4 para pipe 1. 12-08-2018
|
EX_adr_reg_dest => EX_adr_reg_dest2, -- Destination register for the result
|
EX_adr_reg_dest => EX_adr_reg_dest2, -- Destination register for the result
|
EX_ecr_reg => EX_ecr_reg2, -- Effective writing of the result
|
EX_ecr_reg => EX_ecr_reg2, -- Effective writing of the result
|
EX_op_mem => EX_op_mem2, -- Memory operation needed
|
EX_op_mem => EX_op_mem2, -- Memory operation needed
|
EX_r_w => EX_r_w2, -- Type of memory operation (read or write)
|
EX_r_w => EX_r_w2, -- Type of memory operation (read or write)
|
EX_exc_cause => EX_exc_cause2, -- Potential cause exception
|
EX_exc_cause => EX_exc_cause2, -- Potential cause exception
|
EX_level => EX_level2, -- Availability stage of result for bypassing
|
EX_level => EX_level2, -- Availability stage of result for bypassing
|
EX_it_ok => EX_it_ok2 -- Allow hardware interruptions
|
EX_it_ok => EX_it_ok2 -- Allow hardware interruptions
|
);
|
);
|
|
|
U13_bus_ctrl02 : bus_ctrl02 port map (
|
U13_bus_ctrl02 : bus_ctrl02 port map (
|
clock => clock2,
|
clock => clock2,
|
reset => reset,
|
reset => reset,
|
|
|
-- Interruption in the pipeline
|
-- Interruption in the pipeline
|
interrupt => interrupt,
|
interrupt => interrupt,
|
|
|
-- Interface for the Instruction Extraction Stage
|
-- Interface for the Instruction Extraction Stage
|
adr_from_ei => ETC_adr2, -- The address of the data to read
|
adr_from_ei => ETC_adr2, -- The address of the data to read
|
instr_to_ei => CTE_instr2, -- Instruction from the memory
|
instr_to_ei => CTE_instr2, -- Instruction from the memory
|
-- Interface with the MEMory Stage
|
-- Interface with the MEMory Stage
|
req_from_mem => MTC_req2, -- Request to access the ram
|
req_from_mem => MTC_req2, -- Request to access the ram
|
r_w_from_mem => MTC_r_w2, -- Read/Write request
|
r_w_from_mem => MTC_r_w2, -- Read/Write request
|
adr_from_mem => MTC_adr2, -- Address in ram
|
adr_from_mem => MTC_adr2, -- Address in ram
|
data_from_mem => MTC_data2, -- Data to write in ram
|
data_from_mem => MTC_data2, -- Data to write in ram
|
data_to_mem => CTM_data2, -- Data from the ram to the MEMory stage
|
data_to_mem => CTM_data2, -- Data from the ram to the MEMory stage
|
|
|
-- RAM interface signals
|
-- RAM interface signals
|
req_to_ram => ram_req2, -- Request to ram
|
req_to_ram => ram_req2, -- Request to ram
|
adr_to_ram => ram_adr2, -- Address of the data to read or write
|
adr_to_ram => ram_adr2, -- Address of the data to read or write
|
r_w_to_ram => ram_r_w2, -- Read/Write request
|
r_w_to_ram => ram_r_w2, -- Read/Write request
|
ack_from_ram => ram_ack2, -- Acknowledge from the memory
|
ack_from_ram => ram_ack2, -- Acknowledge from the memory
|
data_inout_ram => ram_data2, -- Data from/to the memory
|
data_inout_ram => ram_data2, -- Data from/to the memory
|
|
|
-- Pipeline progress control signal
|
-- Pipeline progress control signal
|
stop_all => stop_all2
|
stop_all => stop_all2
|
);
|
);
|
|
|
U14_clock_gate : clock_gate port map (
|
U14_delay_gate : delay_gate port map (
|
clock_in1 => clock,
|
|
clock_in2 => clock2,
|
|
clock_out1 => clock_out1,
|
|
clock_out2 => clock_out2,
|
|
gate1 => zero,
|
|
gate2 => zero
|
|
);
|
|
|
|
U15_delay_gate : delay_gate port map (
|
|
clock => clock,
|
clock => clock,
|
in1 => DI_bra,
|
in1 => DI_bra,
|
in2 => bra_detect,
|
in2 => bra_detect,
|
in3 => EX_bra_confirm,
|
in3 => EX_bra_confirm,
|
in4 => alea,
|
in4 => alea,
|
in5 => alea2,
|
in5 => alea2,
|
in6 => EX_bra_confirm2,
|
in6 => EX_bra_confirm2,
|
in7 => bra_detect2,
|
in7 => bra_detect2,
|
in8 => DI_bra2,
|
in8 => DI_bra2,
|
in9 => istore,
|
in9 => istore,
|
in10 => istore2,
|
in10 => istore2,
|
in11 => zero,
|
in11 => zero,
|
in12 => zero,
|
in12 => zero,
|
out1 => DI_bra_D,
|
out1 => DI_bra_D,
|
out2 => bra_detect_D,
|
out2 => bra_detect_D,
|
out3 => EX_bra_confirm_D,
|
out3 => EX_bra_confirm_D,
|
out4 => alea_D,
|
out4 => alea_D,
|
out5 => alea2_D,
|
out5 => alea2_D,
|
out6 => EX_bra_confirm2_D,
|
out6 => EX_bra_confirm2_D,
|
out7 => bra_detect2_D,
|
out7 => bra_detect2_D,
|
out8 => DI_bra2_D,
|
out8 => DI_bra2_D,
|
out9 => istore_D,
|
out9 => istore_D,
|
out10 => istore2_D,
|
out10 => istore2_D,
|
out11 => iload,
|
out11 => iload,
|
out12 => iload_D
|
out12 => iload_D
|
);
|
);
|
|
|