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[/] [minsoc/] [branches/] [verilator/] [prj/] [src/] [minsoc_bench.prj] - Diff between revs 128 and 131

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Rev 128 Rev 131
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PROJECT_DIR=(backend bench/verilog bench/verilog/vpi bench/verilog/sim_lib rtl/verilog)
PROJECT_DIR=(backend bench/verilog bench/verilog/vpi bench/verilog/sim_lib rtl/verilog)
PROJECT_SRC=(minsoc_bench_defines.v
PROJECT_SRC=(minsoc_bench_defines.v
minsoc_bench_clock.v
minsoc_bench_clock.v
minsoc_bench.v
minsoc_bench_core.v
minsoc_memory_model.v
minsoc_memory_model.v
dbg_comm_vpi.v
dbg_comm_vpi.v
fpga_memory_primitives.v
fpga_memory_primitives.v
timescale.v)
timescale.v)
 
 

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