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[/] [minsoc/] [tags/] [release-0.9/] [bench/] [verilog/] [minsoc_bench.v] - Diff between revs 8 and 9

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Rev 8 Rev 9
Line 16... Line 16... 
reg spi_miso;
 
reg spi_miso;
 
wire spi_sclk;
 
wire spi_sclk;
 
wire [1:0] spi_ss;
 
wire [1:0] spi_ss;
 
 
 
 
 
wire uart_stx;
 
wire uart_stx;
 
wire uart_srx;
 
reg uart_srx;
 
 
 
 
 
wire eth_col;
 
wire eth_col;
 
wire eth_crs;
 
wire eth_crs;
 
wire eth_trst;
 
wire eth_trst;
 
wire eth_tx_clk;
 
wire eth_tx_clk;

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