URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [tags/] [release-0.9/] [bench/] [verilog/] [minsoc_bench_defines.v] - Diff between revs 7 and 17

Rev 7	Rev 17
Line 6...	Line 6...
`define NO_CLOCK_DIVISION	`define NO_CLOCK_DIVISION
`define POSITIVE_RESET	`define POSITIVE_RESET
`//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER)`	`//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER)`

`define FREQ 25000000	`define FREQ 25000000

`define CLK_PERIOD (1000000000/`FREQ)	`define CLK_PERIOD (1000000000/`FREQ)

`define VPI_DEBUG	`define ETH_PHY_FREQ 25000000
	`define ETH_PHY_PERIOD (1000000000/`ETH_PHY_FREQ) //40ns

`define UART_BAUDRATE 115200	`define UART_BAUDRATE 115200

	`define VPI_DEBUG

//`define VCD_OUTPUT	//`define VCD_OUTPUT

//`define START_UP //pass firmware over spi to or1k_startup	//`define START_UP //pass firmware over spi to or1k_startup

`define INITIALIZE_MEMORY_MODEL //instantaneously initialize memory model with firmware	`define INITIALIZE_MEMORY_MODEL //instantaneously initialize memory model with firmware