| Line 1... |
Line 1... |
+incdir+../../bench/verilog
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+incdir+../../bench/verilog
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+incdir+../../bench/verilog/vpi
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+incdir+../../bench/verilog/vpi
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|
+incdir+../../bench/verilog/sim_lib
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+incdir+../../rtl/verilog
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+incdir+../../rtl/verilog
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+incdir+../../rtl/verilog/minsoc_startup
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+incdir+../../rtl/verilog/minsoc_startup
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+incdir+../../rtl/verilog/or1200/rtl/verilog
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+incdir+../../rtl/verilog/or1200/rtl/verilog
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+incdir+../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog
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+incdir+../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog
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+incdir+../../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog
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+incdir+../../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog
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| Line 13... |
Line 14... |
../../bench/verilog/minsoc_memory_model.v
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../../bench/verilog/minsoc_memory_model.v
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#../../bench/verilog/tb_eth_defines.v
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#../../bench/verilog/tb_eth_defines.v
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#../../bench/verilog/eth_phy_defines.v
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#../../bench/verilog/eth_phy_defines.v
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#../../bench/verilog/eth_phy.v
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#../../bench/verilog/eth_phy.v
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../../bench/verilog/vpi/dbg_comm_vpi.v
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../../bench/verilog/vpi/dbg_comm_vpi.v
|
|
../../bench/verilog/sim_lib/fpga_memory_primitives.v
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../../rtl/verilog/minsoc_top.v
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../../rtl/verilog/minsoc_top.v
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../../rtl/verilog/minsoc_startup/spi_top.v
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../../rtl/verilog/minsoc_startup/spi_top.v
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../../rtl/verilog/minsoc_startup/spi_defines.v
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../../rtl/verilog/minsoc_startup/spi_defines.v
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../../rtl/verilog/minsoc_startup/spi_shift.v
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../../rtl/verilog/minsoc_startup/spi_shift.v
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../../rtl/verilog/minsoc_startup/spi_clgen.v
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../../rtl/verilog/minsoc_startup/spi_clgen.v
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