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[/] [minsoc/] [trunk/] [backend/] [altera_3c25_board/] [minsoc_defines.v] - Diff between revs 93 and 95

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Rev 93 Rev 95
Line 75... Line 75...
`define FPGA_CLOCK_DIVISION             // For Altera ALTPLL, only CYCLONE_III family has been tested.
`define FPGA_CLOCK_DIVISION             // For Altera ALTPLL, only CYCLONE_III family has been tested.
 
 
//
//
// Define division
// Define division
//
//
`define CLOCK_DIVISOR 5         //in case of GENERIC_CLOCK_DIVISION the real value will be rounded 
`define CLOCK_DIVISOR 2         //in case of GENERIC_CLOCK_DIVISION the real value will be rounded 
                            //down to an even value in FPGA case, check minsoc_clock_manager 
                            //down to an even value in FPGA case, check minsoc_clock_manager 
                            //for allowed divisors.
                            //for allowed divisors.
                                            //DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION 
                                            //DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION 
                            //INSTEAD.
                            //INSTEAD.
 
 
//
//
// Reset polarity
// Reset polarity
//
//
//`define NEGATIVE_RESET      //rstn
`define NEGATIVE_RESET      //rstn
`define POSITIVE_RESET      //rst
//`define POSITIVE_RESET      //rst
 
 
//
//
// Start-up circuit (only necessary later to load firmware automatically from SPI memory)
// Start-up circuit (only necessary later to load firmware automatically from SPI memory)
//
//
//`define START_UP
//`define START_UP
 
 
//
//
// Connected modules
// Connected modules
//
//
`define UART
`define UART
`define ETHERNET
//`define ETHERNET
 
 
//
//
// Ethernet reset
// Ethernet reset
//
//
//`define ETH_RESET     1'b0
//`define ETH_RESET     1'b0

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