OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [trunk/] [backend/] [spartan3e_starter_kit/] [minsoc_bench_defines.v] - Diff between revs 70 and 141

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 70 Rev 141
Line 2... Line 2...
`define GENERIC_FPGA
`define GENERIC_FPGA
`define MEMORY_MODEL        //simulation uses a memory model enabling INITIALIZE_MEMORY_MODEL. If you comment this, START_UP might be interesting.
`define MEMORY_MODEL        //simulation uses a memory model enabling INITIALIZE_MEMORY_MODEL. If you comment this, START_UP might be interesting.
`define NO_CLOCK_DIVISION   //if commented out, generic clock division is implemented (odd divisors are rounded down)
`define NO_CLOCK_DIVISION   //if commented out, generic clock division is implemented (odd divisors are rounded down)
//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER)
//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER)
 
 
`define FREQ_NUM_FOR_NS 1000000000
`define FREQ_NUM_FOR_NS 100000000
 
 
`define FREQ 25000000
`define FREQ 25000000
`define CLK_PERIOD (`FREQ_NUM_FOR_NS/`FREQ)
`define CLK_PERIOD (`FREQ_NUM_FOR_NS/`FREQ)
 
 
`define ETH_PHY_FREQ  25000000
`define ETH_PHY_FREQ  25000000
Line 23... Line 23...
`define INITIALIZE_MEMORY_MODEL                 //instantaneously initialize memory model with firmware
`define INITIALIZE_MEMORY_MODEL                 //instantaneously initialize memory model with firmware
                                                                                //only use with the memory model. 
                                                                                //only use with the memory model. 
                                        //If you use the original memory (`define MEMORY_MODEL 
                                        //If you use the original memory (`define MEMORY_MODEL 
                                        //commented out), comment this too.
                                        //commented out), comment this too.
 
 
 No newline at end of file
 No newline at end of file
 
`define TEST_UART
 
//`define TEST_ETHERNET
 
 
 No newline at end of file
 No newline at end of file

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.